MACsec Engine 800G Multi-Channel

Overview

Key Features

• MULTI-CHANNEL MACsec engine
• 800G in 7nm technology
• 400G/600G in 16nm technology
• 100G/200G in reduced area configurations
• Cut-through TDM interface
• 1024-bit (default), 128/256/512-bit (options)
• Up to 64 channels (ports)
• Flexible bandwidth allocation
• FlexE ready
• SA & CLASSIFICATION SCALING
• Pooled SA (up to 4K)
• TCAM internal/external
• CONTROL INTERFACE
• AMBA APB3
• Interrupts (global and per-channel)
• Time-sliced interface with up to 64 channels.
• Aggregate throughput of 400G.
• Supported modes: 1x400G, 4x100G, 8x50G, 16x25G, 40x10G and any combination up to an aggregate throughput of 400Gbps.
• Low-rate modes: 10 Mbit, 100 Mbit and 1G in combination with other rates.
• Each channel has two modes: MACsec and low-latency bypass.
• MACsec PROCESSING FEATURES
• Full SecY processing.
• Compliant with IEEE 802.1AE and all its amendments
• MACsec extensions: passing up to 4 x VLAN tags in clear.
• Automatic MAC SA switching for egress processing.
• Hardware offload for the nextPN and lowestPN update from the host (KaY).
• SA rollover mode for debug purposes.
• DEBUG FEATURES
• EFFICIENT HW/SW INTEGRATION
• FIPS CERTIFICATION
• Support for AES-ECB, AES-CTR, AES-GCM/GMAC transformation for FIPS certification of the crypto core.
• VERIFICATION
• Set of test vectors for chip integration verification.
• Integration test vectors in a human-readable format.
• Python / Verilog based verification environment.
• 100% verification coverage.

Benefits

• Silicon proven MACsec solution with classifier and in-line interface for Multi-channel Ethernet.
• Supports all IEEE MACsec and additional customer specific or proprietary requirements on top of MACsec, related to VLAN parcing, and more.
• Supported by Driver Development Kit, QuickSec MACsec toolkit.

Applications

• Data center, Data center backbone networks, Network appliances providing Enterprise Network Security at Layer-2 using MACsec,
• End-station security solutions for laptops, PCs, printers and network servers.
• Fronthaul and Backhaul, OTN and PON.
• Base stations
• Home gateways

Deliverables

• Documentation
• Hardware Reference and Programmer Manual
• Integration Manual
• Verification Specification
• Programmer and Operations Manual
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Configurations:
• EIP-164d-e-c4-512:
• 512 SAs,
• 256 vPorts,
• 4 channels, Egress
• 2330k gates
• 213.3 bits/clk
• up to 550 MHz
• EIP-164d-i-c4-512:
• 512 SAs,
• 256 vPorts,
• 4 channels, Ingress
• 2650k gates
• 213.3 bits/clk
• up to 550 MHz
• EIP-164d-e-c4-256:
• 512 SAs,
• 128 vPorts,
• 4 channels, Egress
• 2170k gates
• 213.3 bits/clk
• up to 550 MHz
• EIP-164d-i-c4-256:
• 512 SAs,
• 128 vPorts,
• 4 channels, Ingress
• 2380k gates
• 213.3 bits/clk
• up to 550 MHz

Technical Specifications