Low-Jitter PLL is the ultimate-performance ring-oscillator based circuit, achieving best-in-class sub-ps RMS long-term jitter and period jitter performance. Both Integer-N and Fractional-N modes are suitable for clocking precision data converters and SerDes, yet using a fraction of the die area needed for a traditional LC-PLL.
Low-jitter Ring PLL
Overview
Key Features
- 10MHz up to 640MHz input frequency range (65G)
- 14MHz up to 2.8GHz output frequency range (65G)
- Small footprint (0.02mm^2 in 65G
- Integrated Long Term Jitter typically 1ps RMS -- meets requirements for PCIe gen 1, 2, 3 and SATA 1, 2, 3 reference clock
- Phase Noise better than –120dBc/Hz @ 100kHz offset
- Reference Spurs better than –65dBc
- Differential output simplifies output routing
- Separate supply domains for optimal jitter isolation in noisy SoC environments
- Wide range analog supply range (2.25V to 3.63V in 65G)
- Simple digital control interface
Benefits
- No external components required
- No additional supply decoupling required
Deliverables
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note
Technical Specifications
Foundry, Node
TSMC 28nm - 180nm; Global Foundries 28nm - 65nm; SMIC 65nm - 130nm; IBM 65nm - 180nm; ST 90nm
Maturity
Mass Production
Availability
Available Now
GLOBALFOUNDRIES
In Production:
65nm
LPe
Pre-Silicon: 55nm
Pre-Silicon: 55nm
SMIC
Pre-Silicon:
28nm
HK
,
28nm
PS
,
65nm
LL
,
130nm
G
Silicon Proven: 55nm LL
Silicon Proven: 55nm LL
TSMC
In Production:
65nm
GP
Pre-Silicon: 65nm LP
Pre-Silicon: 65nm LP
UMC
Pre-Silicon:
65nm
SP
Silicon Proven: 55nm
Silicon Proven: 55nm