Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO

Overview

The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s). The DB-I2C-MS-Hs-Mode Controller IP Core can also interface a set of Registers within an ASIC / ASSP / FPGA device as well as interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus

The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master / slave devices.

Key Features

I2C Master / Slave with Parameterized FIFO:
Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:

For Transmits, the processor writes the Slave Address & bytes of information into the FIFO, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion
For Receive, the processor writes the Slave Address into the DB-I2C-MS-Hs-ModeI, enables the controller, and waits for an interrupt or polls a status bit signaling completion. The processor then reads the bytes of information from the FIFO.

Small VLSI footprint
Master Controller Modes:
Master – Transmitter
Master – Receiver
Slave Controller Modes:
Slaver – Transmitter
Slave – Receiver
Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, & Repeated Start capabilites
Parameterized FIFO depth for higher performance. Optional 16 or 32-bit processor interface
Supports three I2C bus speeds:
Hs-Mode (3.4 Mbps)
Fast mode plus (1 Mbit/s)
Fast mode (400 Kb/s)
Standard mode (100 Kb/s)
13 sources of internal interrupts with masking control
Compliance with AMBA AXI and I2C specifications:
AMBA AXI Protocol Specification (V2.0)
Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and NXP Rev 0.3 19 June 2007
Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Benefits

The DB-I2C-MS-Hs-Mode Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-MS-Hs-Mode contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-MS-Hs-ModeI Controller. Thus, while the DB-I2C-MS-Hs-Mode is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks. The DB-I2C-MS-Hs-Mode transfers data on the I2C Bus at speeds up to the Hs-Mode of 3.4 Mbps.
Digital Blocks offers Hs-Mode Master/Slave, Master only, and Slave only IP with AXI / AHB / APB / Avalon / Qsys Interfaces. In addition, besides interfacing to a CPU, the I2C Controllers can transfer blocks of data directly between System Memory or Registers and the I2C Bus.

Deliverables

Verilog or VHDL RTL Source or technology-specific netlist.
Comprehensive testbench suite with expected results.
Synthesis scripts.
Installation & Implementation Guide.
Technical Reference Manual.

Technical Specifications

Foundry, Node

Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC

Maturity

Successful in Customer Implementations

Availability

Immediately

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