H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0

Overview

BODA955 is a full HD multi-standard video decoder IP for consumer multimedia products. This IP core is capable of decoding compressed video in a format of AVC/H.264 BP/MP/HP, VC-1 SP/MP/AP, MPEG-1/2, MPEG-4 SP/ASP, H.263 P3, AVS (incl. AVS+), VP8, MVC, and Theora up to Full HD 1920x1088 resolution. Besides, this IP core can perform simultaneous real-time decoding of different multiple format video streams at numerous resolutions.

Key Features

  • Standards
    • AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16
    • MVC SHP L.4.1 Max: 1920x1088; Min: 16x16
    • MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16
    • H.263 Profile 3 Max: 1920x1088; Min: 16x16
    • VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16
    • MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16
    • Sorenson Spark Max: 1920x1088; Min: 16x16
    • VP8 WebM/WebP Max: 1920x1088; Min: 16x16
    • Theora Max: 1920x1088; Min: 16x16
    • AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16
  • Features
    • Frame buffer compression (CFrame)
    • Low delay decoding
    • Configurable IP
    • Programmability
    • Low power consumption
    • Frame-based processing
    • Multi-instances
    • Latency tolerance
    • Burst Write Back
    • Down-scaler (on-the-fly mode)
    • Map converter
    • MPEG-2/4 De-ringing
    • Built-in de-blocking filter
    • A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)

Benefits

  • Provides high performance up to 1080p60
  • Supports MVC(Multi-view Video Coding) for Blu-ray 3D
  • Supports VP8(WebM), Theora as well as H.264 for HTML5
  • Full coverage of streams on a web browser and internet
  • Pre-configurable decoder format enabling SoC designers to optimize for area and power
  • Simultaneous decoding of the multi-channel, multi-format stream.
  • Memory challenge scheme including Tiled buffer map and 2D smart Cache
  • Ultra-low-power hardware architecture using multi-level clock gating
  • Low host CPU resources under 1MIPS
  • Proven performance with a system-level design that minimizes risk and time-to-market

Applications

  • Smartphones, Media Tablet PCs, Portable Multimedia Players, Desktop & Laptop PCs, Digital TVs, Digital Set-top boxes (STBs), Video Game Consoles, surveillance camera, driving recorder, etc.

Deliverables

  • Fully verified synthesizable RTL source code
  • RTL test bench
  • S/W User Guide
  • Datasheet/Integration Guide
  • Verification Guide
  • Evaluation platform

Technical Specifications

Availability
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Semiconductor IP