Enhanced Neural Processing Unit for safety providing 32,768 MACs/cycle of performance for AI applications

Overview

The ASIL B or D Ready DesignWare ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of Advanced Driver Assistance Systems (ADAS) and autonomous vehicle systems that require artificial intelligence (AI) for vision, RADAR, LiDAR and / or sensor fusion.
The NPX6FS NPUs include state-of-the-art hardware safety features including diagnostic error injection, windowed watchdog timers, error classification, and software diagnostic tests as well as safety monitors and lockstep capabilities for safety-critical modules. The processors include dedicated safety mechanisms for ISO 26262 compliance and address the mixed criticality and virtualization requirements of next-generation zonal architectures.
Comprehensive safety documentation, including safety manuals, FMEDA and DFMEA reports, accelerate SoC-level functional safety assessments. These features enable designers to achieve high levels of fault coverage as required for ASIL certifications without a significant effect on performance, power or area compared to the non-ASIL Ready NPX6 NPUs.
The NPX6FS NPUs are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware.
The NPX6FS NPUs are supported by the ASIL D Ready ARC MetaWare MX Development Toolkit for Safety to help simplify the development of ISO 26262-compliant software.

Key Features

Adds hardware safety features to NPX6 NPU, minimizing area and power impact
IEEE 754-compliant vector floating point unit option offers single precision or half precision operations and advanced math functions
Supports ISO 26262 automotive safety standard
IP targets ASIL D compliance to ISO-26262: 2018
Optional software test libraries complement integrated hardware safety features to achieve ASIL B compliance
Supported by MetaWare MX Development Toolkit for Safety with ASIL D Ready compiler and graph mapping tool
Extensive safety documentation eases certification process

Benefits

Scalable real-time AI / neural processor IP with up to 3,500 TOPS performance
Supports CNNs, RNNs/LSTMs transformers, recommender networks, etc
Industry leading power efficiency (up to 30 TOPS/W)
1-24 cores of an enhanced 4K MAC/core convolution accelerator
Tensor accelerator providing flexible activation and support of Tensor Operator Set Architecture (TOSA)
Software Development Kit (Compiler is only one component of the NN SDK) – Automatic mixed mode quantization tools
Bandwidth reduction through architecture and software tool features
Latency reduction through parallel processing of individual layers
Seamless integration with DesignWare ARC VPX vector DSPs
High productivity MetaWare MX Development Toolkit supports Tensorflow and Pytorch frameworks and
ONNX exchange format

Applications

Data center and edge server inference
Smart internet of things (IoT) audio or vision
Digital TVs and still cameras
Smart surveillance
Autonomous vehicles/drones/robotics

Deliverables

The DesignWare ARC NPX6 Processors are delivered as Verilog HDL in the ARChitect IP Library.
The HDL is configured and output from the ARChitect IP Configurator tool.
To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included

Technical Specifications

Maturity

Available on request

Availability

Available

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