eFPGA IP - 100% third party standard cells

Overview

For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is unique in our ability to deliver proven eFPGAs in your selected technology for your specific application.

Key Features

Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
The eFPGA IP Cores are provided as hard IPs (GDSII).
Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.

Benefits

HIGHLY DESIGN ADAPTIVE IP

Support of any technology node, foundry and process option
High LUTs density
Support of any kind of arithmetic block right within the IP
Support of any type and amount of memories, right within the IP
Specific IP specification software available to help defiing the perfect IP for customer SoC and application (Origami Designer)
ASIC like options: power management
Can be rad-hard by design

EASIEST SOC INTEGRATION

No specific interface
Highest yield and reliability
Best testability and cost (TC & FC of 99.7%+). Standard scan chain
Best and simplest verification flow
No change in customer EDA flow. No extra software required

BEST USABILITY

State of the art programming software (Origami Programmer)
Several distribution models possible
No export restrictions

Block Diagram

Applications

Aerospace & Defence

Cryptography
Motor Controls
Adaptive Data conversion
Avoid trojan/hacking at Foundry

Automotive

Autonomous driving - AI for vision applications
Security algorithms over lifetime
Checker and voting logic for lock-steps mode
Motor controls
Battery monitoring systems

HPC / Networking / 5G

AI learning accelerator
Cryptography accelerators
5G base stations evolving standards
Post production customizable CPU
SSD controller
Risk reduction

IoT / IIoT

AI inference at the edge
System time to market and cost reduction
Reduction of variants

Deliverables

Origami Programmer software
GDSII and all files necessary for integration, verification, simulation and test
Datasheets, documention
Can deliver on any CMOS process at any foundry.
Off the shelf IPs available on XFAB XH018 (rad-hard), STM 28FDSOI, GF12LP and TSMC 12FFC.

Technical Specifications

Foundry, Node

Any CMOS process

Maturity

Delivered on 10+ processes at 4 foundries

Availability

Today

GLOBALFOUNDRIES

In Production: 14nm LPP
Pre-Silicon: 12nm , 14nm , 14nm LPE , 14nm LPP , 20nm LPM , 22nm , 22nm FDX , 28nm , 28nm FDSOI , 28nm HPP , 28nm LPH , 28nm SLP , 32nm , 40nm LP , 55nm , 55nm LPX , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV , 180nm , 180nm LL , 180nm LL , 180nm LP , 180nm LP , 250nm , 250nm LPE , 350nm
Silicon Proven: 14nm LPP , 32nm

LFoundry

Pre-Silicon: 150nm , 350nm

Renesas

Pre-Silicon: 40nm , 55nm , 90nm , 150nm

SMIC

Pre-Silicon: 14nm , 28nm , 28nm HK , 28nm HKC+ , 28nm PS , 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm EEPROM , 130nm G , 130nm LL , 130nm LV , 150nm G , 150nm LV , 160nm G , 160nm LL , 180nm EEPROM , 180nm G , 180nm LL , 250nm G

Samsung

Pre-Silicon: 7nm , 8nm , 10nm , 14nm , 28nm FDS , 28nm LPH , 28nm LPP , 32nm LP , 45nm LP , 65nm LP , 90nm LP

Silterra

Pre-Silicon: 90nm , 130nm , 180nm

TSMC

Pre-Silicon: 7nm , 12nm , 16nm , 28nm HPM
Silicon Proven: 28nm HPCP

Tower

Pre-Silicon: 130nm , 180nm , 180nm , 180nm , 500nm

UMC

Pre-Silicon: 14nm , 28nm , 28nm HLP , 28nm HPC , 28nm HPM , 28nm LP , 40nm , 40nm LP , 55nm , 65nm LL , 65nm LP , 65nm SP , 80nm , 90nm G , 90nm LL , 90nm SP , 110nm , 130nm , 150nm , 162nm , 180nm , 250nm , 350nm

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