DDR, Digital Configurable Delay line module

Overview

DDR module configure and set the number of delay elements in half a cycle of the input clock.
Configuration resolution is 4Bits.
The DDR module set , position and align the strobe Tap at configurable fractional input clock cycle after the clock edge.

Key Features

4Bit Configurable delay line, 0.2Nsec to 2Nsec per LSB.
Low power, Low size, MultiTap clock outputs.
Glitch free on configuration

Benefits

Low power, Low size, MultiTap clock outputs.
Glitch free on configuration

Deliverables

GDSII, LEF, SPEC, VERILOG Model, LIB

Technical Specifications

Maturity

Silicon proven, Mass production

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