40G Ultralink D2D PHY for TSMC 5nm

Overview

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

The Cadence® 40G proprietary D2D PHY IP provides an alternative to the high cost of on-die integration, as it caters to growing system-in-package (SiP) applications: CPU to CPU in a multi-core SoC, low-latency coherent interconnect, DSP arrays to process information from lidar, switch fabric integration on multi-chip module (MCM), network ASIC to SerDes PMD on separate die, and chip to in-package optical engine. Today’s emerging hyperscale data centers and a new breed of accelerator / artificial intelligence / machine learning (AI/ML) applications are creating the need for increased per-socket compute power, high bandwidth, low power, and low latency die-to-die interconnectivity.

Key Features

  • Flexible data rate from 20Gbps to 40Gbps
  • Single-ended NRZ signaling scheme
  • BIST features ensure Known Good Die (KGD)
  • Sideband for link management
  • Interoperable between different technology nodes and foundries
  • 1Tbps/mm unidirectional bandwidth
  • Low power and low latency
  • Easy routing and straightforward integration
  • Supports MCMs on organic substrates
  • Better than 1e-15 BER without requiring FEC

Applications

  • High Performance Compute,
  • AI,
  • ML,
  • Servers,
  • Networking,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

Deliverables

  • Integration views: LEF abstract, timing views (.LIB), Verilog behavioral model, gate-level netlist, SDF, DRC, LVS, ANT reports, and GDSII layout and layer map
  • Verilog testbench with example run scripts, demonstration tests, and bus functional models
  • Full documentation set including integration, user, and programmer guides
  • DFT collateral including ATPG generation and setup guidelines and scan abstracts (CTL), High Volume Manufacturing (HVM) kit
  • IPXACT register abstracts, IBIS-AMI kit

Technical Specifications

Foundry, Node
TSMC 5nm
Maturity
Silicon proven
TSMC
Silicon Proven: 5nm
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Semiconductor IP