Optimized for power and area, our line-up of SerDes PHYs, delivering maximum performance and flexibility.
The 16 Gbps Ethernet SerDes PHYs is a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical of copper backplanes and long runs of cable, our 16G MPS PHYs are ideal for networking, telecom and data center systems.
16G Ethernet SerDes PHY - Samsung 14nm
Overview
Key Features
- Duplex lane configurations of x2, x4, and x40
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocols
- A wide range of PLL multiplication supporting low reference clock frequencies
- Tight skew control of 2UI between lanes of the PMA
- Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
- Built-in PRBS pattern generation and checking for standalone loopback testing
- Continuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
Deliverables
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Technical Specifications
Maturity
In Production
Samsung
In Production:
14nm