12G Ethernet PHY in UMC (28nm)

Overview

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification IP, is designed to meet all required features of the PCI Express® (PCIe®) 6.0, 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications. By providing a complete IP solution, Synopsys delivers
optimization across the individual IP to lower latency and ensures that all the IP functions seamlessly together to lower integration risk. The high-performance PCI Express IP solution is optimized for low power, small area and low latency.
The high-quality IP solution has been extensively validated with multiple hardware platforms, PHYs, and PCIe verification suites across a broad range of processes and foundries. With thousands of design wins and products shipping in volume, Synopsys’ expertise in developing and supporting the PCI Express interface enables designers to accelerate time-to-market and achieve silicon success for their advanced SoCs.

Key Features

Physical Coding Sublayer (PCS) block with PIPE interface
Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
Supports x1, x2, x4, x8, and x16 hard macro configurations
Lane margining at the receiver
Optimized High performance analog front-end with adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE) for PCIe 5.0 and ADC/DSP based architecture for PCIe 6.0
Continuous calibration and adaptation (CCA) for a robust performance across voltage and temperature variations
Spread-spectrum clocking (SSC) and PCIe Separate Refclk Independent SSC (SSIS)
Supports PCIe power management features, including L0p, L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external reference clock inputs
PIPE bifurcation as well as PHY macro aggregation for x1 to x16 PHY configurations
Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
Automated Test Equipment (ATE) test vectors for complete at-speed production testing
Each PHY channel contains its own 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)
Support for various form-factors

Benefits

Designed to meet all required features of the PCI Express 6.0 (64 GT/s), 5.0 (32GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
Comprehensive suite of configurable controllers for Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode, and Multi-Port Switch applications
Optimized for low power, small area and low latency
PHYs include advanced built-in diagnostics, enabling at-speed production testing on low-cost digital tester
Automotive Safety Integrity Level (ASIL) B Ready ISO 26262 certified controller and PHY IP
Built-in applications in the verification IP accelerate testbench development
Standards-compliant Synopsys Integrity and Data Encryption Security Modules protect data transfer and are pre-verified with Synopsys Controller IP for PCI Express for fast integration and low risk

Applications

Enterprise computing, storage area networks, networking switches, and routers
Wireless and mobile devices
Industrial, automotive, and IoT
Embedded systems and set-top boxes
Graphics devices
Desktops, laptops, workstations, and servers

Deliverables

Verilog models
Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
GDSII
IP-XACT XML files with register details
ATPG models; IBIS-AMI models
Documentation

Technical Specifications

Foundry, Node

UMC 28nm - HPC, HPC+

Maturity

Available on request

Availability

Available

UMC

Pre-Silicon: 28nm

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