UART with SDLC Function

Overview

The D85C30 - (Serial Communication Controller) is a dual channel USART (Universal Synchro-nous/Asynchronous Receiver/Transmitter) device designed for use with 8 and 16-bit microproces-sors. It functions as a serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide variety of serial com-munications applications. The device contains a variety of new, sophisticated internal functions including on-chip baud rate generators. The D85C30 handles asynchronous formats, synchro-nous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (tele-communication, LAN, etc.). The device can gener-ate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The D85C30 also has facilities for modem control in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The user can configure the D85C30 to handle all synchronous formats regardless of data size, number of stop bits, or parity requirements. D85C30 control is done through access to 14 Write registers and 7 Read registers per channel (the number of the registers varies depending on the version). Within each operating mode, the D85C30 also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort genera-tion and detection, and many other protocol-dependent features.

Key Features

Software compatible with Z85C30

Dual Channel: A, B
Configuration capability
Asynchronous mode:

Asynchronous (x16, x32, or x64 clock
Isochronous (x1 clock)

Character-Oriented mode:

Monosynchronous
Bisynchronous
External Synchronous

Bit-Oriented mode:

SDLC/HDLC
SDLC/HDLC Loop

Complete status reporting capabilities
Receiver data FIFO and Error FIFO
SDLC Frame FIFO
Data encoderdecoder:

NRZ, NRZI
FM0, FM1
Manchester (require external logic)

Line break generation and detection.
Internal diagnostic capabilities:

Loop-back controls for communications link fault isolation
Auto Echo
Break, parity, overrun, framing error simulation

Fully synchronous design with no internal tri-state buffers

Transmission modes:

Synchronous Byte (Bisync) features

5 to 8 Bit characters
Programmable Sync character
Transparent text mode operation
Automatic Sync insertion during Idle
Hardware CRC generation and detection
CRC-16 or CRC-CCITT polynomials

Asynchronous Features

5-8 Bits per character
1, 1,5 and 2 stop bits
Break generation and detection
Parity, overrun and framing error detection
Even, Odd or no parity

Modem controls and indicators

CTS, DSR, DCD and RI lines, usable for modem control or user defined input
DTR and RTS usable for modem control or user defined output

Synchronous SDLC features

1-8 Bits character (transmitter)
5-8 Bits receiver character
Hardware address recognition
Automatic zero insertion and deletion
I-Field residue handling
Automatic flag insertion between messages
Hardware CRC generation and reception

Interrupt system features

Channel functions and timers internally priori-tized
Channel functions and timers generate unique interrupt mode
Prioritized Daisy-chain.

LOOPBACK test mode

Benefits

Rapid prototyping and time-to-market reduction
Design risk elimination
Development costs reduction
Full customization
Global sales network
Technology independence
Professional service
Getting a sillicon proven IP

Applications

Serial Data communications applications
Modem interface
Embedded microprocessor boards

Deliverables

HDL Source Code
Testbench environment

Automatic Simulation macros
Tests with reference responses

Synthesis scripts
Technical documentation
12 months of technical support

Technical Specifications

Request Info