TSN Ethernet Switched Endpoint Controller

Overview

The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.1Qbr), and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint.

The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses.

The TSN-SE is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

Key Features

TSN Ethernet Switched Endpoint

Two Ethernet ports & one host processor port
Suitable for daisy-chained networks such as rings

Low Latency & Flexible Switching

Low-latency Layer-2 Cut-Through Switching
Run-tine switch configuration enables fast response to network changes
802.1Q Tagged VLAN support
Port-based VLAN
Configurable VLAN-PCP to TSN-Queue Mapping (QoS by PCP)
Flexible VLAN and MAC forwarding & filtering
Configurable MAC lookup table for dynamic and static entries & automatic ageing table

TSN Features

Ready for IEEE 802.1as (light-weight software stack available)
Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN Queues
Frame preemption per IEEE 802.1Qbu and IEEE 802.1Qbr (coming soon)

Easy System Integration

AMBA/AXI4 Interfaces

32-bit APB for control/status regis-ters
32-bit AXI4-Stream for packet data

GMII or RGMII, and MIDO Ethernet PHY interface per port
Requires minimal host assistance for its initialization
Complete reference designs available for Altera and Xilinx, including sample application software

Verification IP

The TSN-VIP Ethernet Verification IP package is available for this core

Block Diagram

Applications

The TSN-SE is suitable for the implementation of TSN Ethernet Endpoints in daisy chained networks (e.g. ring topologies) requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, medical, and aerospace applications.

Deliverables

Verilog RTL source code or targeted PFGA netlist
Testbenches
Sample Simulation and Synthesis scripts
Comprehensive Documentation
Lightweight PTP Stack
Device drivers for FreeRTOS and Linux
Example software application

Technical Specifications

Maturity

Silicon Proven

Availability

Now

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