Synchronous Data Link Controller

CoreSDLC provides a high-speed synchronous serial communication controller that utilizes the synchronous data link control (SDLC) protocol. Operation of the CoreSDLC controller is similar to that used in the Intel 8XC152 global serial channel (GSC) device working in SDLC mode under CPU control. Communication with a CPU is via the Advanced Peripheral Bus (APB) interface and three interrupt sources. This enables interfacing CoreSDLC easily with any CPU.

Features:
* Based on Intel's 8XC152 global serial channel working in SDLC mode
* Single and double-byte address recognition
* Address filtering enables multicast and broadcast addresses
* 16-bit (CRC-16) and 32-bit (CRC-32) frame check sequence
* NRZ and NRZI data encoding
* Automatic bit stuffing/stripping
* 3-Byte deep internal receive and transmit FIFOs
* Full or half-duplex operation
* Variable baud rate
* External or internal transmit and receive clocks
* Optional preamble generation
* Programmable interframe space
* Raw transmit and receive testing modes