soft eFPGA IP

Overview

Key Features

• Please refer to the latest datasheet.

Benefits

• Fully integrated into RTL SOC design flow:
• SPC IP RTL/gate simulation.
• Accurate Timing Analysis.
• No black box (LEF/GDSII).
• No verification gap.
• Highly scalable and customizable:
• Pre-existing SPC blocks or
• Custom size SPC blocks.
• 100 to 100k LUTs.
• Multiple SPC’s per chip.
• SPC LUT count is defined with single digit precision to optimize area.
• Technology independent:
• Any CMOS node with digital capacity:
• CMOS 180nm – 14nm
• SOI Rad-Hard
• Any foundry.
• Days/Weeks to deliver.
• No FPGA background required.
• One-time fee to use compilation tools.
• Independent FPGA technology:
• SPC does not copy proprietary commercial FPGA structures (Logic Elements, LUTs, BitRAMs, DSPs …).
• SPC does not rely on commercial FPGA software or third party software, although it is possible to use them.
• ADICSYS’ FPGA software:
• Linux support for ASIC integration.
• Distributable for Linux and Windows end users.
• Compilation Runtime, RTL to bitstream:
• 10k Gates per minute.
• 2X to 4X higher density than competing blocks

Deliverables

• SPC IP comprising:
• Synthesizable RTL.
• Bitstream Loader.
• BIST.
• Synthesis, simulation and STA scripts.
• Place and route scripts and manual.
• Possibility to deliver GDSII in parallel.
• Test patterns.
• ADICSYS FPGA compilation software:
• RTL Parser.
• Synthesis.
• FPGA place & route.
• FPGA bitstream generation.
• Embeddable TCL control shell.
• Operating systems:
• Linux starting with RHEL4.
• Windows starting with XP.
• Documentation, Examples, Training.
• Early SOC definition support.
• General ASIC design assistance.
• SPC customization.
• Standalone FPGA design assistance.

Technical Specifications