Power-On-Reset Intel
Overview
The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
Key Features
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
- Current Consumption1: typ 100nA
- Customizable design for simple SoC integration
- Silicon Area – Please contact Agile Analog
Benefits
- Hysteresis
- - Avoids false resets due to noisy environments
- Configurable thresholds
- - Both upper and lower thresholds are programmable
- - Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions
Applications
- Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
Intel
Maturity
Available on request
Availability
Now
Intel Foundry
Pre-Silicon:
16nm
Related IPs
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- SMIC 0.15um LV Power-On-Reset
- SMIC 0.15um LV Power-On-Reset
- SMIC 0.18um Power-On-Reset
- SMIC 0.18um Power-On-Reset
- Deep capture / high visibility Debug IP for Intel FPGA