Power-On-Reset GlobalFoundries

Overview

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.

Key Features

Start-up Time: max 10us
Configurable Threshold
Programmable Delay
Uses Hysteresis to avoid false resets in noisy environments
Current Consumption: typ 100nA
Customizable design for simple SoC integration
Silicon Area – Please contact Agile Analog

Benefits

Hysteresis
- Avoids false resets due to noisy environments
Configurable thresholds
- Both upper and lower thresholds are programmable
- Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions

Block Diagram

Applications

Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.

Deliverables

Datasheet
Testing and Integration Guide
Verilog Models
Floorplan (LEF)
Timing models (LIB)
Netlist (CDL)
Layout (GDS)
Physical Verification Report
Design Report

Technical Specifications

Foundry, Node

GlobalFoundries 12nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm, 130nm, 180nm

Maturity

Available on request

Availability

Now

GLOBALFOUNDRIES

Pre-Silicon: 12nm , 14nm , 14nm LPE , 14nm LPP , 20nm LPM , 22nm , 22nm FDX , 28nm , 28nm FDSOI , 28nm HPP , 28nm LPH , 28nm SLP , 32nm , 40nm LP , 55nm , 55nm LPX , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV , 180nm , 180nm LL , 180nm LL , 180nm LP , 180nm LP

Request Info