MIPI STP Master IP

Overview

Key Features

• Compliant with MIPI UNIPRO specification version 1.41,1.6 and 1.8
• Supports MIPI M-PHY specification 3.0 and 4.1
• Supports data rate upto 10 Gbps
• Supports multiple connections in L4 Layer and L4 segments
• Supports CPort arbitration at both segment level and packet level
• Supports L2 data frames and control frames
• Supports up to four M-PHY lanes
• Supports MPHY RMMI (10,20,40 bit) Interface in PHY layer
• Supports all power modes for M-PHY in PHY layer
• Supports all types of lane mapping (Lane 0 mapped to 1,2,3 etc)
• Supports link startup as per specs
• Supports Qos monitoring features
• Supports CPort buffer based E2E checking
• Supports Scrambling as per specs
• Supports Controlled segment dropping (CSD), CPort safety valve(CSV)
• Supports complete DME functionality
• Supports interrupt handling for the status of data transfer and error detection in the various layers of Unipro
• Supports PHY adapter layer features:
• -> Transmission and reception of Data Link layer control symbols and data symbols via underlying PHY
• -> Lane distribution and merging in multi-lane ports
• -> Provision of MIPI UniPro power management operating modes
• -> Re-initialization of the PHY TX path
• -> Transmit lane connect/disconnect features
• -> One lane mapping to different lanes
• Supports Data Link layer features:
• -> Frame composition and frame decomposition
• -> Buffering Mechanism
• -> Frame preemption
• -> Triggering of PHY initialization
• -> Two traffic classes by priority-based arbitration
• -> Detect various protocol errors
• Supports Network layer features:
• -> Packet composition and packet decomposition
• -> Packet format recognition
• -> Traffic Class
• -> Error handling
• Supports Transport layer features:
• -> Segmentation and Reassembly
• -> Segment Composition and Segment decomposition
• -> Segment format recognition
• -> Connections management
• -> End-to-End flow control
• -> Error handling
• -> Different CPort arbitration algorithms supported
• Supports various kinds of TX and RX error detection on M-PHY:
• -> Invalid control characters
• -> Timeout conditions
• -> CRC errors

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The MIPI_STP Master interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis and Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User s Guide and Release notes.

Technical Specifications