MIPI SoundWire Slave IP
Overview
The SmartDV MIPI SOUNDWIRE SLAVE IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The MIPI SOUNDWIRE IIP can be implemented in any technology. The MIPI SOUNDWIRE SLAVE IIP core supports the MIPI SOUNDWIRE 1.1x specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Key Features
- Compliant with MIPI SOUNDWIRE version 1.1x Specification.
- Full MIPI SOUNDWIRE Slave functionality.
- Supports slave-to-slave transport
- Supports upto 8 data lanes.
- Supports modified-NRZI data encoding.
- Special internal register for each devices.
- Supports configurable data width of 8,16 and 32.
- Supports configurable PDI count, type, command FIFO depth, data lane
- count, data port memories.
- Supports clearly de-marked clock domains.
- Supports extensive clock gating..
- Provides bi-directional DATA line and unidirectional CLK line.
- Enumeration for device is supported.
- Provides Arbitration mechanism to access the port.
- Provides limited retransmission of Messages.
- Supports Frame layer to interleave Control space and data space in a Sub
- frame.
- Supports all Core Message types.
- User Defined protocol is supported.
- Supports Flow control mechanism.
- Supports Collision Detection for Message channel as well as for Data
- channel.
- Supports various Error Management mechanisms.
- o Error on Segments.
- o Framing error.
- o Parity error.
- o Messaging error.
- o Error on Synchronization.
- o CRC error.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller
- devices
Benefits
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
- The MIPI SoundWire Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis and Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User s Guide and Release notes.