eFPGA IP as a synthesizable RTL core

Overview

Key Features

• Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
• In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
• The eFPGA IP Cores are provided as soft IPs (RTL).
• Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.

Benefits

• HIGHLY DESIGN ADAPTIVE IP
• Support of any technology node, foundry and process option
• High LUTs density
• Support of any kind of arithmetic block right within the IP
• Support of any type and amount of memories, right within the IP
• Specific IP specification software available to help defiing the perfect IP for customer SoC and application (Origami Designer)
• ASIC like options: power management
• Can be rad-hard by design
• EASIEST SOC INTEGRATION
• No specific interface
• Highest yield and reliability
• Best testability and cost (TC & FC of 99.7%+). Standard scan chain
• Best and simplest verification flow
• No change in customer EDA flow. No extra software required
• BEST USABILITY
• State of the art programming software (Origami Programmer)
• Several distribution models possible
• No export restrictions

Applications

• Aerospace & Defence
• Cryptography
• Motor Controls
• Adaptive Data conversion
• Avoid trojan/hacking at Foundry
• Automotive
• Autonomous driving - AI for vision applications
• Security algorithms over lifetime
• Checker and voting logic for lock-steps mode
• Motor controls
• Battery monitoring systems
• HPC / Networking / 5G
• AI learning accelerator
• Cryptography accelerators
• 5G base stations evolving standards
• Post production customizable CPU
• SSD controller
• Risk reduction
• IoT / IIoT
• AI inference at the edge
• System time to market and cost reduction
• Reduction of variants

Deliverables

• Origami Programmer software.
• RTL, documentation and scripts to implement the eFPGA IP.

Technical Specifications