DDRI/II/III/MDDR SSTL/HSTL combo interface without RTT (rectangle) - TSMC 40nm 40LP (CLN40lp)

Overview

Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).

Technical Specifications

Foundry, Node
TSMC 40nm CLN40LP
Maturity
Pre Silicon
Availability
Available
TSMC
Pre-Silicon: 40nm LP
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Semiconductor IP