IP Catalog > Interface IP > Interconnect IP > CXL IP > CXL 3.0 Host Controller

CXL 3.0 Host Controller

Overview

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards.
CXL cards has same form factor as PCIE , and can be used in same pcie slot.
Primesoc CXL controller cores can work in PCIE mode only(when auto negotiation fails) OR CXL mode having pcie transfers handled as IO flits, along with Cache and Mem transfers. The layers specified in CXL specification Transport, Datalink, Physical layers (digital packet) are implemented in PrimeSOC CXL IP along with PIPE interface logic connecting to PHY, AXI Bridging logic, CPI and CXS to connect to applications.

Key Features

  • Compliant to CXL spec V3.X/V2.X.
  • Compliant to PCIE spec 6.0/5.0.
  • CPI Interface support.
  • Compliant to AXI
  • Configurable AXI master, AXI slave. PIPE/FLEX bus.
  • Configurable to work as standalone PCIE DM/CXL DM. Configurable to work as standalone PCIE DM/CXL DM.
  • Configured as PCIE RP/PCIE EP/CXL RP/CXL EP. Native PCIE support.
  • CXL mode / PCIE mode.
  • Static config of PCIE vs CXL.
  • Rate 8/16/32/64 GT/s in CXL mode and 8/16/32/64 in PCIE mode.
  • Configurable X16, X8, X4, X2, X1.
  • Configurable mulltiprotocol of CXL.io/CXL.cache/CXL.mem. Type 1/2/3 CXL devices supported.
  • PCIE Power management using VDM.
  • Configurable credits with granularity of 128 bits. Configurable VCs.
  • ATS support for type1, type2 devices.
  • AER support.
  • Data poisoning.
  • Deferrable writes support.
  • Viral info support.
  • 64B/256B flit support

Deliverables

  • Verilog soft IP
  • Sample testbenc

Technical Specifications

Availability
Immediate
Request Info

Related IPs

×
Semiconductor IP