CSMC 0.18um 1.8v APLL
Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 300MHz to 600MHz. By setting DM[4:0] and DN[6:0] to different values according to different REFIN, CLKO will be locked at the multiples of input frequency.
Key Features
- Process: CSMC 0.18um 1P6M CMOS process
- Supply voltage: 1.8v±10%
- Current: <10mA
- Operating junction temperature: -40°C≤TJ≤+125°C
Technical Specifications
Foundry, Node
CSMC 0.18um