Bandgap Voltage / Current Reference TSMC

Overview

The agileBandGapGP consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of output bias currents can be specified up to a maximum of 16 configurable outputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable, leading to analog IP that is more verifiable, more robust and more reliable.

Key Features

  • Input Voltage Range: PDK VddIO
  • Programmable Output Voltage Range
  • Untrimmed Accuracy: 5%
  • Trimmed Accuracy (single point trim): 0.5%
  • Bias Current Output: 1uA to 100uA
  • PSRR @DC : 50dB typical @DC : 50dB typical
  • @DC : 50dB typical
  • @1MHz : 40dB typical
  • Quiescent Current (Iq): 50uA typical
  • Customizable design for simple SoC integration
  • Integrated Test Bus
  • Silicon Area – Process and feature dependent, please contact Agile Analog for an estimation

Benefits

  • Low Iq
  • - Low current consumption for power sensitive applications
  • Multiple Outputs
  • - Use as a single reference source for your SoC/ASIC

Block Diagram

Bandgap Voltage / Current Reference TSMC Block Diagram

Applications

  • IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

  • Datasheet
  • Testing and Integration Guide
  • Verilog Models
  • Floorplan (LEF)
  • Timing models (LIB)
  • Netlist (CDL)
  • Layout (GDS)
  • Physical Verification Report
  • Design Report

Technical Specifications

Foundry, Node
TSMC
Maturity
Available on request
Availability
Now
TSMC
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Semiconductor IP