“H264EBH” is a highly integrated IP core specifically designed for highest quality video compression. With H.264EBH, encoding high definition content requires 0 processor resources. Further, advanced system prototyping support and flexible SoC integration are key features in our design mentality. H.264 EBH is in full compliance to ISO/IEC 14496-10 (ITU-T H.264 or MPEG-4 part10/AVC) video coding standard. It is designed to offer the maximum level of performance and compression quality at the lowest possible bit-rate with minimal power and silicon requirements. Supported resolutions range from QCIF(176x120) up to 2048x2048 at 30 fps or more. Multi-core instantiation is also possible in order to offer multichannel encoding and maximum performance up to real time full HD. Our core accepts standard digital video input and requires minimal host intervention, constrained to typical register access, in order to produce a fully formed NAL video stream. It can be interfaced to any host through a generic system interface.
Our core’s architecture allows flexible and highly competitive combination of encoding features in order to offer maximum video quality solutions tailored for different FPGA devices or SoC platforms. H.264 EBH supports HDTV video compression (720p) even when implemented in the modest VLSI (0.18um) technology. For FPGA implementations, full D1 resolution at 30 frames per second with a single core is supported.
AVC/H.264 Baseline encoder core
Overview
Key Features
- ISO/IEC 14496-10 (MPEG-4 Part 10), AVC/H.264 Compliant video encoder
- Baseline Profile support
- Single core max. frame resolution up to 2048x2048
- I and P frame types supported
- CAVLC Entropy coding
- Variable bit rate, up to 80 Mbps
- Selection mode decision “low complexity lagrange”
- Intra prediction features
- 16x16 all modes
- 4x4 all modes
- Motion estimation
- Half and quarter pel support
- Search region: +/- 16 Pel (can be extended)
- MB partition possible, up to 4 motion vectors per MB (can be extended to 16 for low resolution)
- De-blocking filter operation supported
- Rate statistics report per data packet
Benefits
- Fully static synchronous design
- Single clock domain
- Single core throughput
- 352x288 x 30 fps @ 20 Mhz
- 720x576/480 x 25/30 fps @ 65 Mhz
- 1280x720 x 20 fps @ 125 Mhz
- Programmable GOP
- Control quality factor/quantization configuration down to Macroblock level
- Configurable external interfaces: video source input, video RAM and microprocessor interface. For example:
- Digital image sensor interface (CCIR-656 compliant)
- DRAM memory interface
- AMBA 2.0 AHB Slave interface
Deliverables
- Encoder Core
- VHDL RTL source code
- Synthesized netlist
- FPGA PROM file
- Synthesis scripts
- Complete VHDL testbench
- Bit accurate model
- Encoder documentation and system integration guide
- Standard and embedded Linux driver supporting 2.4 and 2.6 kernels
- PLUS for integration and verification:
- Hardware demo board
- AVNET Virtex-4 LX
- USB system interface
- H.264 encoder configuration s/w
Technical Specifications
Foundry, Node
0.18, 0.13
Maturity
Silicon Proven: UMC 1P6M, 0.18um - FPGA proven: Single core D1 @ 30 fps in Virtex-4
Availability
Now
UMC
Pre-Silicon:
130nm
,
180nm