The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
- PHY
- ASA Motion Link
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
RISC-V Display Connectivity Subsystem (DCS)
Modern display links have evolved into complex communication systems requiring continuous management of authentication, topology,…
UCIe D2D Adapter & PHY Integrated IP
A UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…
Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.
OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
The CT25210 Topology Discovery (TD) IP coordinates all operations required to perform 10BASE-T1S topology discovery measurements.
Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and produc…
Verification IP for Arm AMBA CHI Protocol
Synopsys Verification IP (VIP) for Arm® AMBA® CHI provides a comprehensive set of protocol, methodology, verification and product…
Verification IP for Arm AMBA ACE Protocol
Synopsys Verification IP (VIP) for Arm® AMBA® ACE provides a comprehensive set of protocol, methodology, verification, and produc…
ForwardEdge’s UCIe IP enables scalable die-to-die connectivity for chiplet-based SoCs.
The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…
The SLVS-EC RX PHY IP is a high-speed, low-power receiver macro compliant with SLVS-EC v3.0 specification, enabling reliable para…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Silicon Creations supports customers in designing ICs for the automotive market by offering its comprehensive product portfolio t…
The TS_CAN_3V3_X8 is a 3.3V CAN transceiver, which supports data rates up to 1Mbps and is compatible with ISO 11898-2 compliant C…
The Controller Area Network (CAN) is a reliable serial bus protocol defined in the Bosch CAN specifications for standard CAN 2.0B…
Simulation VIP for Ethernet UEC
Best-in-class Ethernet Verification IP for your IP, SoC, and System-level Design Testing The Cadence Verification IP (VIP) for Et…
The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and a…
MIPI SoundWire I3S Peripheral IP
The MIPI SoundWire I3S Peripheral IP delivers seamless, low-power, and high-quality audio connectivity for a range of mobile, con…
PCIe PHY and controller solution
Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance.