The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
- PHY
- USB 2.0
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
AXI2CHI · CHI-AXI · CHI-CPI · AXI4-SFI
IO coherency · SLC integration · CHI RN-I
SLC / L3 · 4 MB–32 MB+ · CHI HN-F
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven, fully featured avionics data bus solution purpose-built for defense, ae…
Fully compliant with UCIe v3.0 specification (August 2025); backward compatible with UCIe v2.0, v1.1, and v1.0
SmartDV’s Ethernet 800G PCS (Physical Coding Sublayer) IP Core is engineered to deliver robust and efficient data encoding, align…
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universa…
Fully compliant with OpenGMSL v3.0 specification
Comprehensive Portfolio of Device-Specific PCIe 7.0-CXL 4.0 IP
Fully featured Avionics Full-Duplex Switched Ethernet switch solution purpose-built for safety-critical avionics and aerospace SoC applications requiring deterministic, standards
Silicon-proven, fully featured Avionics Full-Duplex Switched Ethernet end-system solution purpose-built for safety-critical avionics and aerospace SoC applications requiring comp
The VS_DSI2_HOST is a DSI-2 Host Controller that provides a standard, robust, scalable, low-power, high-speed, cost-effective int…
The VS_MIPI_CSI2_DEVICE is a CSI-2 device-side controller that implements the CSI-2 protocol for transmitting data to a CSI-2-com…
Long reach SerDes for Automotive Sensor and Display Applications
Long Reach SerDes for Automotive Sensor and Display Applications
USB 3.2 and DP 1.4 TX Combo PHY
This IP is a USB 3.2 and DP combo PHY which can be flexibly configured as USB mode and DP mode.