Vendor:
Silicon Library Inc.
Category:
USB
USB2.0 PHY
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
Overview
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance. The USB2.0 IP implements a High-Speed USB 2.0 transceiver for use with either host and device function controllers. Compliant with the UTMI+ level 3 specification, the USB2.0 PHY IP integrates mixed-signal circuits to support High-Speed data rate at 480Mbps and is backward compatible to Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates. Targeting mobile and consumer product applications, the USB2.0 PHY IP also supports the supplementary USB Battery Charging specification.
Key features
- Fully compliant with USB 2.0 specifications
- Supports the UTMI+ level 3 specifications
- Supports USB Battery Charging
- Supports 480 Mbps High-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) data transmission rates
- Can be configured as host controller or device peripheral
- Utilizes 8-bit interface at 60MHz operation or 16-bit interface at 30MHz operation
- Supports USB 2.0 Test Mode
- Built-in self test mode to validate high-speed, full-speed and low-speed functionality
- Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks
- Selectable input reference clock frequency (12/24/25MHz)
- Available in both 1-port and 2-port configuration
Block Diagram
Click to open fullscreen
1 /
2
Specifications
Identity
Part Number
USB2.0 PHY
Vendor
Silicon Library Inc.
Type
Silicon IP
Controller / PHY
PHY
Standards & Interfaces
USB Standard
USB 2.0
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Japan
Learn more about USB IP core
Exploring USB Applications and the Impact of USB IP
Understanding USB IP and Its Role in SOC Integration
What Designers Need to Know About USB Low-Power States
In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond the basic features.
New USB 80Gbps Specification Boosts Data Rate, Enables Four Protocols on One Bus
Gervais Fong, Synopsys
New USB Device Class Specification Broadens Use Cases for I3C and I3C Basic
Sharmion Kerley, MIPI Alliance
Frequently asked questions about USB IP cores
What is USB2.0 PHY?
USB2.0 PHY is a USB IP core from Silicon Library Inc. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.