MIPI A-PHY Sink
Long reach SerDes for Automotive Sensor and Display Applications
Overview
A-PHY Sink IP (Link and PHY layers) is a 2-lane SerDes compliant with MIPI A-PHY specification v1.1. Each lane supports Downlink speed up to 8 Gbps and Uplink speed up to 100 Mbps. It targets low-cost high-speed asymmetric data connections in automotive environments where long reach and high reliability are required. Typical applications include advanced driver-assistance systems (ADAS), in-vehicle infotainment (IVI), autonomous driving systems (ADS), and other surround sensors (cameras, displays, LIDARs, etc.).
Key features
- Complies with MIPI A-PHY specification v1.1
- Lane type: 2-lane sink side, asymmetric mode
- Supports Profile-1 and Profile-2: NRZ-8B/10B and PAM4 modulation
- Supports Downlink Gear G1/G2/G3: 2/4/8 Gbps per lane
- Supports Uplink Gear U1: 100 Mbps per lane
- Supports cable length: 15 meters, single-ended 50Ω Coax or differential 100Ω SDP cables
- Supports POC: Power Over Cable (Coax/SDP)
- AEC-Q100 Grade-1 Qualified
- ASIL-B Functional Safety Certified
- Supports wire-bond and flip-chip packages
Block Diagram
Specifications
Identity
Technology
Safety & Qualification
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Single-Protocol PHY IP
What is MIPI A-PHY Sink?
MIPI A-PHY Sink is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.