OpenGMSL Root IP

SmartDV’s OpenGMSL Root IP is a fully featured Gigabit Multimedia Serial Link serializer solution purpose-built for automotive SoC designs requiring reliable, high-bandwidth central compute-side connectivity to edge sensors, cameras, and displays across ADAS, autonomous driving, and in-vehicle infotainment applications. Fully compliant with OpenGMSL v3.0, it delivers complete Root (serializer) functionality supporting forward link data rates up to 12 Gbps and reverse link rates of 187.5 Mbps, with comprehensive support for video streaming, bidirectional sideband data, functional safety, and HDCP content protection, providing a feature-complete OpenGMSL Root implementation for next-generation software-defined vehicle architectures.

As the central compute-side counterpart to the OpenGMSL Leaf deserializer, the Root IP originates video and sensor data streams, distributes them to connected Leaf nodes, and receives reverse link sideband data for bidirectional control and configuration. Its RS-FEC (127,121) encoder for forward link transmission, 9B/10B encoding, scrambling, Reference over Reverse clock reception and synchronization, Precision Time Synchronization, HDCP v1.4 and v2.3 content protection, and functional safety mechanisms give automotive SoC teams a spec-complete, future-ready Root implementation that delivers the reliability and interoperability demanded by next-generation ADAS and autonomous driving zonal compute designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its programmable SERDES interface widths, flexible link topology support, and clean host interface enable fast integration and confident design bring-up across a wide range of automotive process nodes and target applications.

Compliance and Compatibility

• Fully compliant with OpenGMSL v3.0 specification (March 2026)
• Compatible with ADI GMSL2 and GMSL3 technology implementations
• Optional support for HDCP v1.4 and HDCP v2.3 content protection
• Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Full OpenGMSL Root Functionality – Complete serializer implementation per OpenGMSL v3.0 supporting forward link rates of 3 Gbps (Link Rate 1), 6 Gbps (Link Rate 2 NRZ and Link Rate 3 PAM4), and 12 Gbps (Link Rate 4) with 187.5 Mbps reverse link
• Comprehensive Video Format Support – RGB 4:4:4 (16/18/24/30/36 bpp), YUV 4:2:2 (16/20 bpp), YCbCr 4:2:2 (16/20 bpp), YCbCr 4:2:0 (16/20 bpp), RAW (8/10/12/14/16/20 bpp), and Byte-based (8 bpp)
• Full-Duplex Multi-Stream Support – Unidirectional video/sensor streams and bidirectional data for Ethernet, SPI, I2C, UART, I2S/TDM audio, PDM audio, GPIO streams, and infoframes
• RS-FEC Forward Error Correction – RS-FEC (127,121) encoder for forward link transmission for reliable high-speed automotive SerDes operation
• Advanced Signal Processing – 9B/10B encoder and scrambler for forward link and 9B/10B decoder and descrambler for reverse link operation
• Flexible SERDES Interface – Programmable parallel SERDES widths of 20, 40, and 80 bits for forward link and 10-bit for reverse link operation
• Flexible Link Topology – Splitter, aggregation, and daisy-chain link topology support with standard and fast link startup
• Precision Time Synchronization – PTS support and Reference over Reverse (RoR) clock reception and synchronization using reverse link reference clock
• Content Protection – HDCP v1.4 and v2.3 encryption and decryption for video and audio stream protection
• Functional Safety – FuSa mechanisms per OpenGMSL v3.0 for ASIL-rated automotive safety applications
• Power Management – Sleep and Standby low power state support for power-efficient automotive central compute node operation