The USB 2.0 Hub core is designed for flexibility and ease of use and is technology independent.
- USB
- now
- USB 2.0 Compliant
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The USB 2.0 Hub core is designed for flexibility and ease of use and is technology independent.
USB 2.0 Host Controller (EHCI)
The USB 2.0 Host controller is designed for flexibility and ease of use and facilitates implementation of a wide variety of appli…
SMTPE-292 Scrambler & Descrambler / Framer
The SMPTE292 core set, coupled with the AMCC S8401/S8501 serializer/deserializer chipset is fully compliant to the SMPTE 292M spe…
Integrates MAC IP to a broad range of PHY and SerDes IP
The silicon proven USB host controller is compliant with USB 1.1 and OHCI 1.0 Specifications.
The USB 2.0 soft core facilitates data transmission up to 480 Mbps and is ideally suited for high-speed devices like CD-Rom drive…
CAN 2.0 B Compatible Network Controller
The logiCAN core provides all features expected from the standard CAN network controller.
Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
AXI2CHI · CHI-AXI · CHI-CPI · AXI4-SFI
IO coherency · SLC integration · CHI RN-I
SLC / L3 · 4 MB–32 MB+ · CHI HN-F
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven, fully featured avionics data bus solution purpose-built for defense, ae…
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
SmartDV’s Ethernet 800G PCS (Physical Coding Sublayer) IP Core is engineered to deliver robust and efficient data encoding, align…
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universa…
Gigabit Multimedia Serial Link serializer solution purpose-built for automotive SoC designs requiring reliable, high-bandwidth central compute-side connectivity to edge sensors,
Comprehensive Portfolio of Device-Specific PCIe 7.0-CXL 4.0 IP