Comprehensive Portfolio of Device-Specific PCIe 7.0-CXL 4.0 IP
Panmnesia's Link Acceleration Unit (LAU) IP is a purpose-built hardware block that accelerates device-specific, end-to-end communication over CXL. The IP significantly reduces time-to-market for diverse types of hardware design such as memory expander devices (CXL type 3), accelerators (CXL type 1/2), and CPUs.
Key Features
Our product in more details
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Specification |
PCIe 7.0/CXL 4.0 Backward compatible with CXL 3.2, 2.0, 1.1, and previous versions of PCIe |
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Optimized system support |
Optimized for CXL CPU, CXL Switch, CXL GPU/xPU, CXL DRAM, etc. |
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Supported subprotocols |
CXL.io, CXL.mem, CXL.cache P2P communication support Dynamic Capacity Device (DCD) support Device COHerence engine (DCOH) support Back-invalidate snoop coherence support Bias-based coherency model support Snoop filter support Protocol conversion options support |
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Supported device types |
CXL type 1/2/3 device support Multi-Logical Device (MLD) support Multi-Headed Device (MHD) support Fabric-Attached Memory (FAM) support (G-FAM, LD-FAM) |
Available Device & Sub Protocols
Overview of protocol compatibility across different CXL endpoint types and configurations
| Protocols | Type 1 Endpoint | Type 2 Endpoint | Type 3 Endpoint | Root Complex |
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| Description | Accelerator devices with their cache connected to the CXL network (e.g., ASIC, xPU) | Accelerator devices with their memory connected to the CXL network (e.g., GPU, xPU) | Memory expander devices providing memory capacity to the CXL network | CPU being root of the virtual hierarchy in the CXL network |
| CXL.io | ✓ | ✓ | ✓ | ✓ |
| CXL.cache | ✓ | ✓ | ✓ | |
| CXL.mem | ✓ | ✓ | ✓ |
✓ Indicates protocol support • ✗ Protocol not supported • Protocol compatibility varies by implementation
Hardware-Managed Cache Coherency
Manage cache coherency without software intervention. LAU IP supports hardware-automated handling of cache coherency features, such as back invalidation, for diverse types of devices.
Device-Specific Hardware Optimization
Minimize communication latency and deliver fast, deterministic responsiveness in latency-critical workloads. LAU IP offloads device-specific processes into hardware, enabling real-time execution when every nanosecond counts.
Best-In-Class Latency & Power Consumption
Achieve exceptional latency and power efficiency with a purpose-built, optimized architecture. Maximize performance-per-watt for power-constrained and performance-critical designs.
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Link Acceleration Unit is a CXL IP core from Panmnesia listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.