AFDX 1G End-System IP

SmartDV’s AFDX 1G End-System IP is a silicon-proven, fully featured Avionics Full-Duplex Switched Ethernet end-system solution purpose-built for safety-critical avionics and aerospace SoC applications requiring complete AFDX network node implementation. Fully compliant with ARINC 664 Part 7 and IEEE 802.3-2018, it delivers a complete end-system implementation supporting full-duplex Ethernet at 10/100/1000 Mbps with integrated PHY management via MDIO, Virtual Link traffic shaping, and comprehensive TSN feature support — providing a proven, production-ready AFDX end-system foundation for next-generation avionics network designs.

As a complete end-system implementation rather than a standalone MAC, the IP integrates MDIO Clause 22 and Clause 45 PHY management alongside the full AFDX MAC feature set including Virtual Link Bandwidth Allocation Gap enforcement, frame replication and elimination, traffic scheduling, class-based flow control, and cut-through support. Its comprehensive TSN feature set, detailed per-Virtual-Link statistics, and independently configurable TSN features give avionics SoC teams a production-tested, spec-complete AFDX end-system that meets the stringent determinism and reliability requirements of DO-178C and DO-254 certified avionics designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its fully synthesizable architecture, GMII/RGMII/MII physical interface support, and AXI4 Stream packet data interface enable fast integration and confident design bring-up across a wide range of avionics process nodes and target applications.

Compliance and Compatibility

• Fully compliant with ARINC 664 Part 7 (AFDX)
• Fully compliant with IEEE 802.3-2022 for 10/100/1000M Ethernet
• Optional support for IEEE 802.1Qbu and IEEE 802.3br frame preemption
• Optional support for IEEE 802.1Qbv and IEEE 802.1Qav traffic scheduling
• Optional support for IEEE 802.1CB frame replication and elimination
• Optional support for IEEE 802.1Q class-based flow control
• Supports MDIO Clause 22 and Clause 45 for PHY management
• Configurable SoC interface supporting AXI-4 Stream and custom wrappers for seamless integration
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Full AFDX End-System Functionality – Complete ARINC 664 Part 7 end-system implementation at 10/100/1000 Mbps with full-duplex Ethernet operation per IEEE 802.3-2018
• MDIO PHY Management – MDIO Clause 22 and Clause 45 interface support for complete PHY configuration and management within the end-system
• Virtual Link Traffic Shaping – Bandwidth Allocation Gap (BAG) enforcement for deterministic, bounded-latency data transfer across Virtual Links
• TSN Feature Support – IEEE 802.1Qbv traffic scheduling, IEEE 802.1Qav credit-based shaping, and IEEE 802.1CB frame replication and elimination for robust time-sensitive networking
• Frame Preemption Support – IEEE 802.1Qbu and IEEE 802.3br Interspersing Express Traffic for ultra-low latency priority frame delivery
• Class-Based Flow Control – IEEE 802.1Q class-based FIFO with support for up to 8 traffic classes for deterministic QoS management
• Ultra-Low Latency Cut-Through – Cut-through switching support for minimal frame delivery latency in time-critical avionics applications
• Comprehensive Statistics – Detailed per-Virtual-Link message count and network statistics per ARINC 664 specification
• Flexible Physical Interface – GMII, RGMII, and MII interface support with programmable IPG, preamble length, configurable TX/RX FIFOs, and AXI4 Stream 32-bit packet data interface