eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 …
- SD / eMMC Controller
- Silicon proven in mass production
- Now
- eMMC 5.1, JEDEC JESD-84-B51
System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
These IP cores include components such as timers, DMA controllers, GPIO, interrupt controllers, and watchdog timers, enabling efficient coordination between processing units and peripherals.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 …
Digital Power Grid Overlay -- 20% to 40% Total Digital Dynamic Power Reduction
All electronic systems that use CMOS digital circuits generate EM noise and currents (overlap current) as an undesired byproduct …
Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market.
The PCIe-NVMe SSD controller platform is compliant with NVM Express 1.2 specification and targets for both enterprise and client …
MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS
UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobil…
MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro
Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification.
CC-100IP-MB Electric Vehicle Mileage Booster IP
CC-100IP-MB re-cycles system noise and surge current, preventing the deep discharge of system DC-Link and Reservoir Capacitors, r…
Real Time Clock (RTC) Master core
NetTimeLogic’s RTC Master Clock is a full hardware (FPGA) only implementation of a synchronization core allowing to read and writ…
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass …
The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications.
The Stream Buffer Controller IP Core is optimized for Intel (Altera) and Xilinx FPGAs and implements a versatile Stream to Memory…
Deep capture / high visibility Debug IP for Intel FPGA
The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…
Deep capture / high visibility Debug IP for Xilinx FPGA
The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…
Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
The Serial ATA Host Controller IP Core provides an interface to highspeed serial link replacements for the parallel ATA attachmen…
The Stream Buffer Controller IP Core implements a versatile Stream to Memory Mapped DMA bridge with 16 independent streams.
The Enclustra Universal Drive Controller IP Core enables the easy addition of drive control capabilities to existing or future FP…
iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0.
SDIO Slave controller facilitates the design of SDIO cards and reduces the development time.
The SD Memory Slave controller is designed to reside within SD Memory card.
ATA/ATAPI Controller core provides interface between a host system and a ATA/ATAPI device.