Vendor: Signature IP Corporation Category: Coherency

Proxy Cache

IO coherency · SLC integration · CHI RN-I

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Overview

Maintains coherency for IO devices accessing cached memory: allows non-coherent DMA masters to participate in the CHI coherency protocol without a full cache implementation.

Key specifications

Purpose IO coherency
Protocol CHI RN-I
Integration With SLC/L3
Masters Non-coherent DMA
Deployment Compute silicon
Sign-off Siemens Questa

Technical details

CHI node RN-I
Snoops Handled on behalf
Configuration APB3
DMA masters Configurable
Silicon Compute silicon
Works with SLC / L3

Key features

  • IO coherency participation
  • Integrates with SLC/L3
  • CHI RN-I interface

Block Diagram

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Specifications

Identity

Part Number
Proxy Cache
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Contact Signature IP Corporation

Learn more about Coherency IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

Frequently asked questions about Coherency Interconnect IP cores

What is Proxy Cache?

Proxy Cache is a Coherency IP core from Signature IP Corporation listed on Semi IP Hub.

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