Semiconductor IP Articles

Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM

By Manan Patel, Google LLC

October 2, 2026

U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC

By Federico Villani, ETH Zurich

October 2, 2026

S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM

By Wu Yang, Southern Methodist University

September 29, 2026

MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²

By Alessandro Nadalini, University of Bologna

September 29, 2026

Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices

By Antonio Carreño, Universidad Politecnica de Madrid

September 28, 2026

Toki: Profiling HBM Performance on FPGA Systems with RISC-V Soft Cores and PCIe Host DMA Traffic

By Andrea Galimberti, Politecnico di Milano

September 23, 2026

VSpector: Specification-Driven Bug Detection for RISC-V CPUs

By Tianyu Jia, Renmin University of China

September 22, 2026

Demystifying Gate-Level Localization of RTL Trojans

By Navid Nader Tehrani, University of Wisconsin-Madison

September 22, 2026

Can Agents Design Better Chips with a Higher Level Abstraction?

By Zijian Ding, UCLA

September 21, 2026

FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity

By Nicolas Chauvaux, TU Delft

September 18, 2026

MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators

By Dong Liu, University of California, Los Angeles

September 18, 2026

Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs

By Ramana Ranganatham, Rochester Institute of Technology

September 17, 2026

SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment

By Samuel Moussa, Minia University

September 16, 2026

Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing

By Yu-Wei Fan, Princeton University

September 15, 2026

REACH: Controller-Managed Long-Span ECC for HBM AI Inference

By Rui Xie, Rensselaer Polytechnic Institute

September 14, 2026

FPGA Acceleration of Fully Homomorphic Encryption with Adaptive Key Switching

By Zhihan Xu, University of Southern California

September 10, 2026

AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors

By Sharjeel Imtiaz, Tallinn University of Technology

September 10, 2026

LLM Inference on IMC-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism

By Yimin Wang, National University of Singapore

September 7, 2026

AI-Assisted Design of a Post-Quantum Cryptographic Accelerator: A Deployed-Silicon Case Study

By Jungmin Park, Lucid Motors

September 4, 2026

Hardware Acceleration of Block-Diffusion LLM for Edge Devices

By Wei-Hsing Huang, Georgia Institute of Technology

September 3, 2026