Semiconductor IP Articles

Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference

By Rúben Teixeira, IObundle, Lda

August 14, 2026

HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA

By Christophe Clienti

August 13, 2026

Hybrid ASIC-FPAA Fabric for Performance Security Trade-off

By Ziyi Chen, Drexel University

August 12, 2026

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

By Mohammed Sajjad Jafri, University of Waterloo

August 11, 2026

A Low-Latency ASIC Architecture for Real-Time Line Segment Detection

By Amir Hossein Jalilvand, Iran University of Science and Technology

August 10, 2026

BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision

By Ang Li, Delft University of Technology

August 5, 2026

A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

By Amirhossein Zarei, INRS-EMT

August 3, 2026

Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching

By Wiebren Wijnstra, University of Twente

July 30, 2026

SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow

By Andrija Nešković, Universität zu Lübeck

July 29, 2026

A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition

By Zhifan Song, Sorbonne University

July 28, 2026

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

By Benjamin Hubinet, CEA-Leti

July 27, 2026

Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge

By Chanda Gupta, Indian Institute of Technology Roorkee

July 23, 2026

Si-GT: Fast Interconnect Signal Integrity Analysis For Integrated Circuit Design Via Graph Transformers

By Yuting Hu, University at Buffalo

July 22, 2026

Hardware Mechanisms to Dynamically Throttle AI Performance

By Haiyue Ma, Princeton University

July 22, 2026

SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

By Weiying Wang, Chinese Academy of Sciences

July 21, 2026

New Number Formats for FFT IP Cores in Optical OFDM Transceivers

By Lukas Krupp, RPTU University Kaiserslautern-Landau

July 21, 2026

Reducing Power Consumption of Embedded Dynamic Memories with ECCs

By Wenqing Song, EPFL

July 20, 2026

NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

By Jiajun Hu, Arizona State University

July 17, 2026

A 32-channel event-based bio-signal analog front-end with adaptive delta and pulse frequency encoding

By Narayanan Shyam, University of Zurich

July 16, 2026

Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems

By Xiaorang Guo, Technical University of Munich

July 13, 2026