Reconfiguring System-Level Protection Through Bounded Delegation in RISC-V MCUs By Luís Cunha, University of Minho November 13, 2026
SkipLane: Write-Once, Conflict-Free Accumulation for Zero-Skipping CNN Engines on FPGAs By Aditya Saboo, Indian Institute of Technology Indore November 12, 2026
Priority-Aware Deficit Round Robin for AXI4 Bandwidth Fairness in ASAP-7nm Process By Tasmin Khan, Bangladesh Univ. of Eng. & Tech. November 11, 2026
Atik: A Shared-Mesh Transformer Accelerator for RISC-V By Ahmed Zeer, Yildiz Technical University November 9, 2026
GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow By Zirui Ma, Chinese Academy of Sciences November 6, 2026
Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor By Yihang Dai, Nanjing University November 5, 2026
A Cross-Domain Matrix Engine for Signal Processing and Deep Neural Net Inference By Mehdi Safarpour, University of Oulu November 4, 2026
LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation By Leo Itoh, The University of Tokyo October 30, 2026
Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors By Debleena Das, Indian Statistical Institute October 26, 2026
Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library By Mohamed Gharib, University of Illinois Chicago October 20, 2026
A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET By Oscar Castañeda, ETH Zurich October 20, 2026
Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains By Murali Emani, Argonne National Laboratory October 19, 2026
The Era of Vibe Tapeout: Dark Age or Golden Age for Analog Circuit Design? By Kentaro Yoshioka, Keio University October 15, 2026
Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips By Ataberk Olgun, ETH Zurich October 15, 2026
BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors By Habibur Rahaman, University of Florida October 13, 2026
RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design By Awani Khodkumbhe, Qualcomm Technologies October 13, 2026
Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA By Seungki Hong, ETH Zurich October 12, 2026
Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study By Alireza Abolhasani Zeraatkar, University of California, Davis October 12, 2026
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller By Harsh Songara, ETH Zürich October 9, 2026