Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
October 26, 2026
Semiconductor IP Articles
Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
October 20, 2026
A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
October 20, 2026
Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains
October 19, 2026
Minimum RISC-V: Maximum FPGA Efficiency
October 16, 2026
The Era of Vibe Tapeout: Dark Age or Golden Age for Analog Circuit Design?
October 15, 2026
Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips
October 15, 2026
BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
October 13, 2026
RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
October 13, 2026
Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
October 12, 2026
Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
October 12, 2026
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
October 9, 2026
A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
October 8, 2026
An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
October 8, 2026
A Formal Security Analysis of CAN XL
October 6, 2026
A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
October 5, 2026
ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
October 5, 2026
Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
October 2, 2026
U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
October 2, 2026
S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
September 29, 2026
