SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC
June 10, 2026
Semiconductor IP Articles
A 65 nm Trustworthy Hypoglycemia Forecasting Engine Achieving 11.3 nJ per Inference
June 9, 2026
ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
June 8, 2026
ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
June 5, 2026
OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
June 3, 2026
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
June 3, 2026
CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
June 1, 2026
A Time Scaling Theory for Multi-Layer Electronic Systems
May 29, 2026
GenAI-Driven Approach to RISC-V Supply Chain Exploration
May 25, 2026
HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
May 21, 2026
Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM
May 20, 2026
Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
May 19, 2026
TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
May 18, 2026
Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
May 13, 2026
A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
May 13, 2026
ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
May 12, 2026
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
May 12, 2026
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
May 11, 2026
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
May 6, 2026
EPAC: A RISC-V Accelerator from the European Processor Initiative
May 5, 2026