Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification By Davis Ranney, Northeastern University July 2, 2026
CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems By Enrico Zelioli, ETH Zurich July 1, 2026
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research By Angela Cui, University of California, Berkeley June 29, 2026
Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon By Enrico Zelioli, ETH Zurich June 26, 2026
Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming By Poornima Kumaresan, Indian Institute of Technology Delhi June 23, 2026
Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs By David Peter Federl, University Duisburg-Essen June 19, 2026
CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety By Yuecheng Wang, University of Cambridge June 18, 2026
AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing By Shirui Zhao, KU Leuven June 17, 2026
InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment By Niccolò Lentini, Politecnico di Torino June 16, 2026
SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC By Sonu Kumar, Indian Institute of Technology Indore June 10, 2026
A 65 nm Trustworthy Hypoglycemia Forecasting Engine Achieving 11.3 nJ per Inference By Boyang Cheng, University of Notre Dame June 9, 2026
ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs By Adiwena Putra, KAIST June 8, 2026
ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training By Haihang Xia, The University of Sheffield June 5, 2026
OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs By Denis Lebold, University of Duisburg-Essen June 3, 2026
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees By Lorenzo Leone, ETH Zurich June 3, 2026
CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST By Kaustav Goswami, University of California June 1, 2026
GenAI-Driven Approach to RISC-V Supply Chain Exploration By Nenad Petrovic, Technical University of Munich May 25, 2026
HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip By Pei-Huan Tsai, Columbia University May 21, 2026