Agentic AI-based Coverage Closure for Formal Verification By Sivaram Pothireddypalli, Infineon April 29, 2026
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors By Weiying Wang, University of Chinese Academy of Sciences April 27, 2026
RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification By Nick Andreasyan, Automotive Safety Lab April 21, 2026
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities By Tanvir Rahman, University of Florida April 20, 2026
A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting By Fang-Chi Chang, National Yang Ming Chiao Tung University April 15, 2026
SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation By Zicheng He, University of California, Los Angeles April 13, 2026
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks By Marco Bertuletti, ETH April 8, 2026
Assertain: Automated Security Assertion Generation Using Large Language Models By Shams Tarek, University of Florida, Gainesville April 6, 2026
VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems By Akram Ben Ahmed, National Institute of Advanced Industrial Sciences and Technology April 3, 2026
A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators By Luca Colagrande, ETH Zurich April 1, 2026
Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification By Antonino Armato, Robert Bosch March 31, 2026
SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research By Zehra Karadağ, Ruhr University Bochum March 30, 2026
An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks By Mohammad Javad Sekonji, Shahid Bahonar University of Kerman March 23, 2026
Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings By Jie Lei, Universitat Politècnica de València March 20, 2026
A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency By Junyi Liu, University of Maryland March 18, 2026
SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks By Kanishka Gunawardana, University of Peradeniya March 13, 2026
An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS By Qiyue Chen, University of Science and Technology of China March 12, 2026
A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA By Neelesh Gupta, University of Southern California March 11, 2026
VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration By Max Wipfli, ETH Zurich March 9, 2026