Semiconductor IP Articles

Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge

By Chanda Gupta, Indian Institute of Technology Roorkee

July 23, 2026

Si-GT: Fast Interconnect Signal Integrity Analysis For Integrated Circuit Design Via Graph Transformers

By Yuting Hu, University at Buffalo

July 22, 2026

Hardware Mechanisms to Dynamically Throttle AI Performance

By Haiyue Ma, Princeton University

July 22, 2026

SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

By Weiying Wang, Chinese Academy of Sciences

July 21, 2026

New Number Formats for FFT IP Cores in Optical OFDM Transceivers

By Lukas Krupp, RPTU University Kaiserslautern-Landau

July 21, 2026

Reducing Power Consumption of Embedded Dynamic Memories with ECCs

By Wenqing Song, EPFL

July 20, 2026

NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

By Jiajun Hu, Arizona State University

July 17, 2026

A 32-channel event-based bio-signal analog front-end with adaptive delta and pulse frequency encoding

By Narayanan Shyam, University of Zurich

July 16, 2026

Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems

By Xiaorang Guo, Technical University of Munich

July 13, 2026

FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers

By Hubert Dymarkowski, University of Glasgow

July 6, 2026

LIB-TRAP: Standard Cell Library Hardware Trojan Risk Assessment and Prevention

By Harish Kumar Dharavath, University of Arizona

July 3, 2026

Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification

By Davis Ranney, Northeastern University

July 2, 2026

CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems

By Enrico Zelioli, ETH Zurich

July 1, 2026

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research

By Angela Cui, University of California, Berkeley

June 29, 2026

Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon

By Enrico Zelioli, ETH Zurich

June 26, 2026

Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming

By Poornima Kumaresan, Indian Institute of Technology Delhi

June 23, 2026

LLM4RTL: Tool-Assisted LLM for RTL Generation

By Jing Jin, UC Riverside

June 22, 2026

Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs

By David Peter Federl, University Duisburg-Essen

June 19, 2026

CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety

By Yuecheng Wang, University of Cambridge

June 18, 2026

AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing

By Shirui Zhao, KU Leuven

June 17, 2026