Fully featured Avionics Full-Duplex Switched Ethernet switch solution purpose-built for safety-critical avionics and aerospace SoC applications requiring deterministic, standards
- Ethernet
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Fully featured Avionics Full-Duplex Switched Ethernet switch solution purpose-built for safety-critical avionics and aerospace SoC applications requiring deterministic, standards
Silicon-proven, fully featured Avionics Full-Duplex Switched Ethernet end-system solution purpose-built for safety-critical avionics and aerospace SoC applications requiring comp
The VS_DSI2_HOST is a DSI-2 Host Controller that provides a standard, robust, scalable, low-power, high-speed, cost-effective int…
The VS_MIPI_CSI2_DEVICE is a CSI-2 device-side controller that implements the CSI-2 protocol for transmitting data to a CSI-2-com…
Long reach SerDes for Automotive Sensor and Display Applications
Long Reach SerDes for Automotive Sensor and Display Applications
USB 3.2 and DP 1.4 TX Combo PHY
This IP is a USB 3.2 and DP combo PHY which can be flexibly configured as USB mode and DP mode.
USB 3.0 and PCIe 2.0 Combo PHY
The USB 3.0 SuperSpeed and PCI Express Combo PHY is a programmable IP compatible with the PHY Interface for the PCI Express Archi…
The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in process that implements the In…
1.25 Gbps-16 Gbps HSS for Supporting Multiple Protocols
The 12.5 Gbps to 16 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols
The 1.25 Gbps to 12.5 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY
The DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface.
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface.
VBO Receiver with four and eight lanes for video communication
VBO Transmitter with 8 lanes and 16 lanes for video communication
UCIe Controller (CHI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
UCIe Controller (AXI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
Die-to-Die (D2D) Interface for Chiplet Application
Compliant with the UCIe Specification Revision 1.1