The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
- SPI / QSPI XSPI
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion…
SLI UHS-II PHY Analog IP consists of a mixed-signal SERDES supporting both Full Duplex and Half Duplex modes.
Ethernet Switch VLAN 5x100M
Ethernet Switch/Router L2/L3/MPLS 12x10G
This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and rou…
Ethernet Switch/Router Enterprise 9x10G + 2x25G
This is a L2 switch and an IP/MPLS router with ACL engines.
Ethernet Switch/Router Datacenter ToR 32x100G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 32 ports, with up to 100 Gbit of bandwidth per port.
The USB device core is compliant with revision 1.1.
Protocol controller IP for a CAN FD light responder node
The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.It supports CAN FD light respon…
Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
The XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, o…
The Network on Chip (NOC) technology redefines typical NOC capabilities as it extends the on-chip network beyond chip(let) bounda…
USB Full Speed Transceiver
PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
Controller + ATC + ATS + DTI · CXL.io · CXL.cache · CXL.mem · Memory pooling
Compliant with CXL Specification 2.0
Compliant to PCI Express base specification 5.0
Next-generation CMOS image sensor interface, SLVS-EC v3.0, is implemented in FPGAs SLVS-EC v3.0 Rx IP is an interface IP core tha…