MIPI DSI Host Controller

The VS_DSI2_HOST is a DSI-2 Host Controller that provides a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices. This DSI-2 interface IP core is fully compliant with MIPI Alliance Standard for Display Serial Interface 2 (DSI-2) Version 2.2. It supports both D-PHY (up to 4 lanes) and C-PHY (up to 3 trios) interfaces with configurable PPI widths for high-speed and low-power operation. The IP provides an enhanced DPI supporting both video and command modes with programmable signal polarity and configurable pixel throughput (1 or 4 pixels per cycle), and it supports a wide range of video mode formats per DSI-2 v2.2, including various YCbCr, RGB, and compressed pixel streams up to 48-bit. In addition to BIST (color bar) mode, comprehensive error detection is implemented, covering PHY, packet, protocol, and FIFO status.

• MIPI Alliance Specification compliant with D-PHY Version 3.0
• MIPI Alliance Specification compliant with C-PHY Version 2.1
• MIPI Alliance Standard compliant with Display Serial Interface 2 (DSI-2) Version 2.2
• Supports D-PHY de-skew, alternative calibration
• Supports configurable 4 ppc or 1 ppc in DPI interface, and both video and command modes
• Command mode supports 16/18/24/30/36-bit RGB using DPI interface as 1 pixel per cycle or 4 pixels per cycle
• Supports arbitrary command packet size which can be divided by total pixels per frame
• Video mode supports all pixel formats (up to 48-bit DPI data width) in DSI-2 v2.2
• Supports APB3 control register with shadow configuration mechanism
• Supports command among video mode and enhanced Display Pixel Interface
• Supports BIST mode (color bar), timeout error detection, and error report from peripheral
• Interfaces with optional MIPI D-PHY or C-PHY following PHY Protocol Interface (PPI)
• Supports D-PHY: 8-bit, 16-bit, or 32-bit PPI (programmable)
• Supports C-PHY: 16-bit, 32-bit, or 64-bit PPI (programmable)
• Supports up to MIPI D-PHY TX 4 data lanes and C-PHY TX 3trios
• Supports D-PHY high-speed and low-power operation, C-PHY high-speed and low-power operation
• Supports programmable scrambling
• Supports programmable polarity for enhanced DPI signals
• Configurable SRAM size