Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-effic…
- PCI Express
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-effic…
Dolphin Technology provides AMBA® Bus IPs for AMBA connection, includes AXI4, AXI3, APB and AHP.
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
I²S Controller is designed to transfer audio data to and from Audio codec.
Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one o…
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…
1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
XEC is a high performance 1000M/100M/10M Ethernet Controller IP.
The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
The Nuclei Universal Serial Bus (USB) Controller is compliant with the USB 2.0 Specification to support high-speed,full-speed or …
CMOS camera.
Serial Audio Interface/Inter-IC Sound
The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configur…
The Improved Inter Integrated Circuit (I3C) is part of a group of communication protocols defined by the MIPI Alliance.
I2C (Inter-Integrated Circuit) bus Interface serves as an interface between the microcontroller and the serial I2C bus.
Controller Area Network with Flexible Data rate
The XKAN module is a communication controller implementing the CAN protocol specification version 2.0 part A, B and CAN with Flex…
General Purpose Input/Output controller
The Nuclei LGPIO (Logic general-purpose I/Os) describes the operation of the Logic General Purpose Input/Output Controller(LGPIO).
Full duplex asynchronous communications
The USART (Universal Synchronous Asynchronous Receiver Transmitter) offers a flexible means of full-duplex data exchange with ext…