Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
Discover Synopsys 64G UCIe IP for energy-efficient, high-bandwidth die-to-die connectivity in advanced multi-die AI and HPC designs.
Vendor:
SmartDV Technologies
Category:
UCIe
CHI to UCIe Bridge IP
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universa…
Overview
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universal Chiplet Interconnect Express (UCIe) standard, facilitating high-bandwidth, low-latency communication in multi-die and chiplet-based designs. This bridge IP is ideal for next-generation SoCs requiring cache-coherent communication across die boundaries while leveraging the open UCIe ecosystem.
Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its modular architecture ensures easy integration into diverse system architectures, helping accelerate time-to-market for advanced heterogeneous computing platforms.
Compliance and Compatibility
- Fully compliant with UCIe 1.0, 1.1, and 2.0 specifications and ARM AMBA5 CHI protocol
- Compatible with Standard and Advanced UCIe packages, in both Root Complex and Endpoint modes
- Compatible with all major EDA synthesis, simulation, and linting flows
Block Diagram
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Benefits
- Seamless Chiplet Interoperability – Bridges AMBA CHI-based SoCs with UCIe-compliant chiplets, supporting UCIe versions 1.0, 1.1, and 2.0 for multi-die integration
- High-Speed Data Exchange – Supports link speeds of 4, 8, 12, 16, 24, and 32 GT/s with UCIe clock frequencies up to 4 GHz and sideband speeds up to 800 MHz
- Protocol Translation with Integrity – Maintains CHI protocol semantics across Request, Home, and Slave Nodes with full support for CHI-D transaction types, opcodes, flow control, and cache coherency
- Configurable for System Needs – Offers flexible lane configurations (16, 32, 64 lanes), supports Endpoint and Root Complex modes, and accommodates Standard and Advanced UCIe packages
- Flit Format & Retry Support – Enables raw and streaming protocol flit formats including latency-optimized 256B formats, with CRC, retry, and flit delay support for robust data handling
- Advanced SoC and Cache Control – Includes fine-grain transaction-level control, programmable cache models with speculative reads, stashing, snoop filtering, and protocol-level reorder and retry features
- Optimized for Integration – Includes standard bus interfaces and CHI-to-UCIe handshake, sideband messaging, mailbox access, link initialization retry, and vendor-defined message support
Specifications
Identity
Part Number
CHI to UCIe Bridge IP
Vendor
SmartDV Technologies
Type
Silicon IP
Standards & Interfaces
UCIe Version
UCIe 1.0
,
UCIe 1.1
,
UCIe 2.0
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about UCIe IP cores
What is CHI to UCIe Bridge IP?
CHI to UCIe Bridge IP is a UCIe IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.