Embedded Security explained: Advanced Encryption Standard (AES)
June 9, 2026
Expert Perspectives on Semiconductor IP and SoC Design
Technical analysis and industry insights covering semiconductor IP and SoC integration.
Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
June 9, 2026
Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
June 8, 2026
From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
June 5, 2026
Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP
June 4, 2026
Why nonce reuse can break AES-GCM security in embedded systems
June 4, 2026
PQSecure™-Agility Earns NIST CAVP Validation
June 3, 2026
Mitigating the Single-Source Trap
June 2, 2026
Showcase at AutoSens US: Integration of TicoRAW into dSPACE high performance data logging solution enables seamless workflow
June 2, 2026
What Makes Ethernet IP Truly Automotive-Grade
June 1, 2026
Arasan 16-bit xSPI/PSRAM Controller and PHY: Enabling High-Performance Embedded Memory Systems
June 1, 2026
Using SystemC TLM Modeling To Solve AI Data Movement Challenges
May 29, 2026
Accelerating SoC Development with Agnisys Silicon IP Portfolio Automation
May 29, 2026
Ten Years in CiA, Over Two Decades of CAN IP Reliability
May 29, 2026
AI in Design Verification: From Experimentation to Measurable Capability
May 28, 2026
Agentic AI-powered Arm Metis advances security vulnerability discovery in software
May 28, 2026
AES in embedded systems: Understanding the most important AES modes
May 28, 2026
UWB and 6G: Why Precision Sensing Will Define the Next Wireless Revolution
May 28, 2026
Your NPU Learned to Listen
May 28, 2026
AI-Accelerated Vulnerability Discovery: An Emergency in Software Security. Is Hardware Next?
May 27, 2026