AI-Driven Development: Why Verification Matters More Than Ever
September 3, 2026
Expert Perspectives on Semiconductor IP and SoC Design
Technical analysis and industry insights covering semiconductor IP and SoC integration.
Why schematic-correct designs fail at advanced nodes
September 3, 2026
How Agentic AI Turns IC Engineers into Architects
September 2, 2026
DDR5 MRDIMM Gen2: The Missing Link in Scaling AI Infrastructure
September 1, 2026
How Cache Coherency Simplifies AI Software
August 31, 2026
Multiple neuromorphic chips, one grid, no new middleware
August 31, 2026
Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
August 28, 2026
A scalable, shader-programmable vector graphics GPU core for low-power MCUs
August 27, 2026
Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
August 26, 2026
Embedded Security explained: Digital signatures
August 26, 2026
Hardware security verification must go beyond functional testing
August 25, 2026
Have Benchmarks, Now What?
August 25, 2026
Automatic Generation of a Network-on-Chip Interconnect
August 24, 2026
Is Pergrammable a Word?
August 21, 2026
Implementing I3C Host Controller support in the open source I3C Core
August 20, 2026
SystemLens Gives System Engineers Real-Time Visibility Into Hidden Silicon Issues Under Functional Tests
August 19, 2026
As Vehicles Become Data Centers: Why Interface IP Integration Matters in SoC Design
August 18, 2026
Implementing a multi-stage secure boot chain on an Efinix Titanium Ti375
August 18, 2026
Last-Level Caches Matter Even More in the HBM Era
August 17, 2026
Audio AI at the Edge: When the Tiniest Devices Learn to Listen
August 17, 2026
