Estimating the silicon area of specialty I/Os
November 12, 2026
Expert Perspectives on Semiconductor IP and SoC Design
Technical analysis and industry insights covering semiconductor IP and SoC integration.
TDISP and Confidential Computing: Extending the PCIe Chain of Trust
November 11, 2026
AI-Generated UVM Testbenches from SoC Specifications
November 11, 2026
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity
November 10, 2026
Agentic AI Should Fit the Way You Engineer
November 10, 2026
Listening at the Speed of Memory: Live Speech Recognition on Chimera
November 10, 2026
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
November 5, 2026
From photon to actuation: How physical AI is redefining embedded compute
November 5, 2026
Secure Boot for embedded Linux on Efinix Ti375C529: Getting started with KiviBoot-Linux
November 5, 2026
Akida in High-Frequency Trading: The Smart Signal Layer
November 5, 2026
Cadence Expands Sovereign AI in Europe: From Chips to AI Factories
November 4, 2026
PCI Express Security and TEE Integration, Part 2 - Protecting PCIe Traffic
November 3, 2026
How to Use AI Agents to Streamline Code Reviews
November 3, 2026
The Memory Challenge of Physical AI
November 3, 2026
How Arm is redefining the PC ecosystem
November 2, 2026
JPEG XS TDC: what temporal differential coding brings
November 2, 2026
Jevons’ Paradox and the Silicon Roadmap
November 2, 2026
How IDS-AI Helps Make Your Specifications Golden
November 2, 2026
AI can design the chip, manufacturing it is harder
October 30, 2026
Designing for What Comes Next in AI
October 29, 2026
