AFDX 1G Switch IP

SmartDV’s AFDX 1G Switch IP is a fully featured Avionics Full-Duplex Switched Ethernet switch solution purpose-built for safety-critical avionics and aerospace SoC applications requiring deterministic, standards-compliant AFDX network switching. Fully compliant with ARINC 664 Part 7 and IEEE 802.3-2022, it delivers complete AFDX switch functionality at 10/100/1000 Mbps with frame filtering, Virtual Link traffic shaping, comprehensive TSN support, and ultra-low latency cut-through switching — providing a feature-complete AFDX network switch for next-generation avionics network infrastructure designs.

Designed to address the full breadth of AFDX switch requirements, the IP implements the complete ARINC 664 frame filtering mechanism covering Ethernet frame size validation (64 to 1518 bytes), Frame Check Sequence validity checking, frame length error detection, and Ethernet line size validation (84 to 1538 bytes), alongside Virtual Link Bandwidth Allocation Gap enforcement, traffic scheduling, frame replication and elimination, and class-based flow control across 8 traffic classes. Its independently configurable TSN features, detailed per-Virtual-Link statistics, programmable IPG and preamble length, and configurable transmit and receive FIFOs give avionics network infrastructure teams a spec-complete AFDX switch implementation suited for the most demanding safety-critical airborne network designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its fully synthesizable architecture, GMII/RGMII/MII physical interface support, and AXI4 Stream 32-bit packet data interface enable fast integration and confident design bring-up across a wide range of avionics process nodes and target applications.

Compliance and Compatibility

• Fully compliant with ARINC 664 Part 7 (AFDX)
• Fully compliant with IEEE 802.3-2022 for 10/100/1000M Ethernet
• Optional support for IEEE 802.1Qbu and IEEE 802.3br frame preemption
• Optional support for IEEE 802.1Qbv and IEEE 802.1Qav traffic scheduling
• Optional support for IEEE 802.1CB frame replication and elimination
• Optional support for IEEE 802.1Q class-based flow control
• Configurable SoC interface supporting AXI-4 Stream and custom wrappers for seamless integration
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Full AFDX Switch Functionality – Complete ARINC 664 Part 7 switch implementation at 10/100/1000 Mbps with full-duplex Ethernet operation per IEEE 802.3-2022
• ARINC 664 Frame Filtering – Complete frame filtering per ARINC 664 specification including Ethernet frame size (64 to 1518 bytes), FCS validity, frame length error, and Ethernet line size (84 to 1538 bytes) validation
• Virtual Link Traffic Shaping – Bandwidth Allocation Gap (BAG) enforcement for deterministic, bounded-latency data transfer across all Virtual Links
• TSN Feature Support – IEEE 802.1Qbv traffic scheduling, IEEE 802.1Qav credit-based shaping, and IEEE 802.1CB frame replication and elimination for robust time-sensitive networking
• Frame Preemption Support – IEEE 802.1Qbu and IEEE 802.3br Interspersing Express Traffic for ultra-low latency priority frame delivery
• Class-Based Flow Control – IEEE 802.1Q class-based FIFO with support for up to 8 traffic classes for deterministic QoS management
• Ultra-Low Latency Cut-Through – Cut-through switching support for minimal frame delivery latency in time-critical avionics network applications
• Comprehensive Statistics – Detailed per-Virtual-Link message count and network statistics per ARINC 664 specification
• Flexible Physical Interface – GMII, RGMII, and MII interface support with programmable IPG, preamble length, configurable TX/RX FIFOs, and AXI4 Stream 32-bit packet data interface