Learn more about Protocol Bridge IP core
MesoLink™ enables a PCIe/CXL device under test to run at its own native generation and lane width as well as timing agnostic while the system side runs at full FPGA SerDes speed — to plug-n-play validation on FPGA prototyping and emulation platforms.
Next-Generation NoC Pioneer Demonstrates Industry-Leading PCIe Controller IP and Scalable IO Subsystems on Siemens Veloce proFPGA CS Platform
New CXL 3.2 IP and Flex Bus Port Technology Delivers Enhanced Performance for Next-Generation Data Center, AI, and HPC Applications
SignatureIP, the pioneer of next generation interconnect and interface solutions, announces that its Networks-on-Chips (NoCs) provide the necessary infrastructure to efficiently connect and manage RISC-V CPUs in complex chip designs.
Available at iNoCulator.ai, it is the first cloud-based platform for design of a Network on Chip (NoC). A NoC provides the interconnect infrastructure between key compute, storage, memory and I/O blocks in a semiconductor chip.
SignatureIP, the pioneer of next generation NoC tools, has announced the availability of its new PCIe® Gen 6 Controller IP that works from Gen 1 to Gen 6.