Hybrid Memory Cube (HMC) interface IP cores provide the controller, serial interface, and protocol logic needed to connect SoCs, FPGAs, and specialized processors to HMC memory devices. HMC combines vertically stacked DRAM dies with a logic base die, interconnected through through-silicon vias (TSVs), to support high-bandwidth memory access in a compact footprint.
HMC interfaces use high-speed, full-duplex serial links and a packet-based protocol to exchange commands and data between host devices and memory cubes. Multiple links and independently accessible memory vaults support parallel transactions for demanding high-performance computing, networking, and data processing applications.
This catalog brings together HMC interface and verification IP for implementing and validating HMC-based memory subsystems. Solutions can be compared based on supported HMC specification revision, serial lane rate, link width, host interface, error detection and retry capabilities, and ASIC or FPGA compatibility. HMC verification IP supports protocol compliance testing, traffic generation, and error scenario validation.
Hybrid Memory Cube Verification IP
The IP offers an easy-to-use and complete verification solution for SoC's using the HMC Host Controller at the IP level or system-level.
HMC Synthesizable Transactor provides a smart way to verify the HMC component of a SOC or a ASIC in Emulator or FPGA platform.
HMC Memory Model provides an smart way to verify the HMC component of a SOC or a ASIC.
The HMC Verification IP provides an effective & efficient way to verify the HMC components of an ASIC/FPGA or SoC i.e.
The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect …