Vendor: Signature IP Corporation Category: Coherency

System-Level Cache

SLC / L3 · 4 MB–32 MB+ · CHI HN-F

Overview

Last-level shared cache reducing off-chip traffic between CPU clusters, AI accelerators, and main memory. Configurable size and associativity.

Key specifications

Size 4 MB to 32 MB+
Associativity NWAY configurable
Protocol CHI HN-F
Prefetch Stash transactions
Integration Proxy cache
Deployment Compute silicon

Technical details

CHI attachment HN-F port
Ways Configurable NWAY
Line size 64 bytes
Stash Supported
ECC Single-bit correct
Silicon Compute silicon

Key features

  • 4 MB to 32 MB+ configurable
  • NWAY set-associative
  • Stash transactions for prefetch
  • CHI HN-F port attachment

Block Diagram

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Specifications

Identity

Part Number
System-Level Cache
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Learn more about Coherency IP core

Frequently asked questions about Coherency Interconnect IP cores

What is System-Level Cache?

System-Level Cache is a Coherency IP core from Signature IP Corporation listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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