Debug and trace IP cores help designers observe, control, and analyze system behavior during development, validation, and in-field diagnostics. These semiconductor IP blocks are used in CPUs, MCUs, complex SoCs, automotive platforms, and safety-critical embedded systems.
Explore debug and trace IP solutions for run control, real-time visibility, software optimization, post-silicon validation, and standards-based processor debug integration.
Deep capture / high visibility Debug IP for Intel FPGA
The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…
Deep capture / high visibility Debug IP for Xilinx FPGA
The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…
IEEE1149.1-2001 JTAG access port
The Beyond TAP Controller is a fully IEEE 1149.1-2001 compatible JTAG Test Access Port (TAP) Controller.
The AMBA ATB Verification IP provides an effective & efficient way to verify the components interfacing with the AMBA ATB interfa…
AMBA ATB Verification IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC.
AMBA ATB Synthesizable Transactor
AMBA ATB Synthesizable Transactor provides a smart way to verify the AMBA ATB component of a SOC or a ASIC in Emulator or FPGA pl…
AMBA ATB Assertion IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC.
The Tessent Embedded Software Development Kit (ESDK) is a set of software libraries designed to be compiled and run on an embedde…
Empowering Design Quality with Harmony Trace
Harmony Trace by Arteris, the Design Data Intelligence Solution for complex SoC and System-of-SoCs projects.
Tessent Automotive IC debug and optimization
Vehicles are becoming complex systems approaching billions of lines of code.
Tessent AI IC debug and optimization
The multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications provide unique challe…
Tessent Static Instrumentation
The Tessent Embedded Static Instrumentation module provides a nonintrusive mechanism for code instrumentation.
Tessent SoC debug and optimization
Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs.
Emulation of RF and channel impairments in Verilog
The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmissi…
Synopsys Verification IP (VIP) for Arm® AMBA® ATB™ provides a comprehensive set of protocol, methodology, verification, and produ…
Cadence provides a mature and comprehensive Verification IP (VIP) for the Trace Bus (ATB) specification which is part of the Arm®…
Reset Verification IP can be used to generate reset signals in testbench.
Clock Verification IP can be used to generate clock signals in testbench.
System Integrated Logic Analyzer (System ILA)
The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer which can be used to monitor the inter…
The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals …