Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be configured for dual-mode applications supporting runtime-selectability between device and host mode. The CXL controller supports Synopsys’ MultiStream architecture, for maximum throughput efficiency across various link widths and payloads. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 128GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. Support for the latest specification based features such as Port Based Routing, 256B Latency Optimized FLIT, 4 Retimer Support and Bundled Port Assist give the controller the ultimate flexibility and feature capabilities. The Synopsys CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with user-friendly application interfaces (CXS or Native for CXL.cm) or industry standard AMBA interfaces (AXI or Native for CXL.io), for a wide range of SOCs including CPUs, SSDs, NICs, AI Accelerators, Automotive and other applications.
The Synopsys Integrity and Data Encryption (IDE) Security Modules for CXL 2.0, CXL 3.x and CXL 4.0 are standards-compliant and pre-verified with the Synopsys Controller IP to help designers protect data transfer in their SoCs against tampering and physical attacks. The security modules meet the required high bandwidth with optimal area and latency as low as zero cycles for CXL.cache/.mem protocols in skid mode. Synopsys CXL Controllers with IDE security support the TEE Device Interface Security Protocol (TDISP) for CXL.io and the CXL TEE Security Protocol (CXL-TSP) for CXL .cache/.mem. TDISP and TSP standardized frameworks define how to secure the interconnect between virtual machine hosts and devices, regardless of where the data center resides or who has access to the servers inside. Synopsys CXL Controllers with IDE enable designers to build full TDISP and TSP support in their hyperscale SoCs and mitigate against data and system attacks, addressing the challenges of secure I/O virtualization. Learn about the broad portfolio of Security Solutions for Interfaces.
The Synopsys CXL Controller IP is based on the Synopsys PCI Express Controller IP which has been silicon validated in thousands of designs with multiple hardware platforms, PHYs, and PCIe verification suites, thereby reducing risk and accelerating time-to-market. Synopsys offers a comprehensive and robust CXL IP solution proven in volume production and successfully implemented in a wide range of applications and works diligently to ensure interoperability throughout the broader ecosystem of standards based solutions to ensure 1st time silicon success.
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CXL Controller With HPC Features (Spec Version 3.0 and Above) is a CXL IP core from Synopsys, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.
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