UCIe 3.x Controller IP

SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most demanding SoC and multi-die system designs requiring ultra-high-bandwidth, low-latency die-to-die connectivity across AI accelerators, high-performance computing, and next-generation data center chiplet architectures. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, it delivers complete UCIe controller functionality supporting PCIe, CXL, and streaming protocols including AXI, CXS, and CHI at speeds up to 64 GT/s across 16, 32, and 64 lane configurations, providing a feature-complete die-to-die interconnect foundation for next-generation chiplet-based system designs.

As the semiconductor industry accelerates its transition to modular chiplet architectures, UCIe v3.0 doubles the maximum die-to-die bandwidth of v2.0 while adding runtime recalibration, priority sideband messaging, and low-power sideband operation. SmartDV’s UCIe 3.x Controller IP implements the complete UCIe v3.0 feature set spanning the Protocol Layer with AXI, CXL, CXS, PCIe, and CHI bridges, D2D Adapter Layer with Flit Pack, Flit Retry, CRC, and Parity, and APB Sideband with Protocol and Credit management, giving chiplet system teams a spec-complete, future-ready UCIe controller that addresses the most demanding AI and data center multi-die interconnect requirements.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture, clock gating mechanism, and RDI TX/RX interface to the PHY enable fast integration and confident design bring-up across a wide range of advanced process nodes and chiplet packaging configurations.

Compliance and Compatibility

• Fully compliant with UCIe v3.0 specification (August 2025); backward compatible with UCIe v2.0, v1.1, and v1.0
• Supports PCIe, CXL, AXI, CXS, and CHI protocol stacks
• Supports Standard Package and Advanced Package UCIe configurations
• Configurable SoC interface supporting AXI, APB, and custom wrappers for seamless integration
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Full UCIe 3.x Controller Functionality – Complete UCIe stack implementation per UCIe v3.0 supporting Endpoint and Root Complex modes with Standard and Advanced Package configurations
• Multi-Protocol Support – PCIe, CXL, and streaming protocols including AXI, CXS, and CHI with dedicated protocol bridges and FDI interfaces per protocol
• Ultra-High-Speed Multi-Lane Support – 16, 32, and 64 lane configurations at 4 GT/s through 64 GT/s with UCIe clock frequencies from 500 MHz to 8 GHz
• Comprehensive FLIT Format Support – Raw Format, 68B FLIT, Standard 256B End Header, Standard 256B Start Header, Latency-Optimized 256B without Optional Bytes, and Latency-Optimized 256B with Optional Bytes
• Complete D2D Adapter Layer – Flit Pack, Flit Retry, Transmitter and Receiver CRC, Transmitter and Receiver Parity, and D2D Pack/Unpack/Control for robust die-to-die data integrity
• Comprehensive Sideband Infrastructure – Sideband messaging for link training and parameter exchange, Sideband Mailbox for read/write configuration, 800 MHz sideband data speed, priority sideband messaging, and all Vendor Defined Sideband messages
• Advanced Link Management – UCIe Retimer support, Flit CRC, Flit Retry, clock gating, all handshake mechanisms, DLLP field checking, Data Link Feature Exchange, and Link Power Management
• Multi-Stack Protocol Support – Multi-Stack protocol support with runtime recalibration for flexible chiplet topology integration across complex multi-die system architectures