Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Multi-Protocol PHY

USB 3.2 and DP 1.4 TX Combo PHY

This IP is a USB 3.2 and DP combo PHY which can be flexibly configured as USB mode and DP mode.

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Overview

This IP is a USB 3.2 and DP combo PHY which can be flexibly configured as USB mode and DP mode. The USB 3.2 Gen 2x2 PHY mode provides a complete range of USB 3.2 Gen2 host and peripheral applications at up to 20 Gbps. The USB 3.2 Gen 2x2 PHY mode also integrates high-speed mixed signal circuits to support Gen2 (10 Gbps) and Gen1 (5 Gbps). The DP PHY mode provides data rates of 1.62 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps compatible with one lane, two lanes, and four lanes.

Key features

  • Fully compatible with:
    • USB 3.2 SuperSpeed Plus: Universal Serial Bus 3.2 Specification, Revision 1.1
    • VESA DisplayPort (DP) Standard, Version 1.4
    • VESA DisplayPort Alt Mode on USB Type-C Standard, Version 1.0a
  • Supports data rates:
    • USB 3.2 SuperSpeed Plus: 10 Gbps (Gen 2) and 5 Gbps (Gen 1)
    • DP Alt data rates: 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps
  • Configurable lanes for multiport Type-C USB 3.2 SS+ and DP modes
  • Supports all USB 3.2 power management modes
  • Spread spectrum clock (SSC) and data scrambling to minimize EMI
  • Supports a wide range of reference clocks:
    • 12/19.2/20/24/25/26/27/30/38.4/40/48/50/52/54/60/100/108/200 MHz
  • Multiple loopback and compliance test modes
  • Built-in BIST pattern generator and checker with programmable modes for stand-alone tests
  • On-chip Eye Opening Monitor (EOM) to measure the eye diagram at the RX side
  • Adaptive and configurable RX continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • Programmable TX feed-forward equalization (FFE)
  • 8b/10b and 128b/132b encoding and decoding implemented in hardware
  • Supports LFPS generation and detection
  • IEEE standards 1149.1 and 1149.6 (JTAG) boundary scan for internal visibility and control
  • APB and I2C interfaces to access the internal registers for different applications
  • Supports flip-chip packaging

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Specifications

Identity

Part Number
USB 3.2/DP 1.4 TX Combo PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

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Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about Multi-Protocol PHY IP core

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Frequently asked questions about Multi-Protocol PHY IP cores

What is USB 3.2 and DP 1.4 TX Combo PHY?

USB 3.2 and DP 1.4 TX Combo PHY is a Multi-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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