Semiconductor IP Articles Archive - Page 6 of 231

Pipeline Automation Framework for Reusable High-throughput Network Applications on FPGA

By Jean Bruant, OVHcloud

January 22, 2026

A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)

By eMemory & PUFsecurity

January 21, 2026

IMS: Intelligent Hardware Monitoring System for Secure SoCs

By Wadid Foudhaili, Universität zu Lübeck

January 19, 2026

Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs

By Mostafa Darvishi, Evolution Optiks Limited

January 14, 2026

Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications

By Vijay Pratap Sharma, Indian Institute of Technology Indore

January 14, 2026

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference

By Nuntipat Narkthong, Northeastern University

January 13, 2026

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

By Rui Xie, Rensselaer Polytechnic Institute

January 7, 2026

Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory

By Guan-Cheng Chen, National Cheng Kung University

January 6, 2026

ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update

By Zhe Su, University of Zurich and ETH Zurich

December 26, 2025

A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

By Darja Nonaca, ETH Zurich

December 22, 2025

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

By Mostafa Darvishi, ÉTS, Montreal

December 17, 2025

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

By Juncheng Huo, Chinese Academy of Sciences

December 16, 2025

Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval

By Grant Bosworth, Rochester Institute of Technology

December 15, 2025

Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension

By Songqiao Cui, KU Leuven

December 10, 2025

ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes

By Dilli Babu Porlapothula, International Institute of Information Technology

December 9, 2025

In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

By Sanwar Ahmed Ovy, North Dakota State University

December 8, 2025

David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?

By Shashwat Shankar, Indian Institute of Technology

December 5, 2025

RoMe: Row Granularity Access Memory System for Large Language Models

By Hwayong Nam, Seoul National University

December 3, 2025

Analog Foundation Models

By Julian Büchel, IBM Research

December 2, 2025

Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators

By Jason Yik, Harvard University

December 1, 2025