Semiconductor IP Articles Archive - Page 4 of 228

In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

By Sanwar Ahmed Ovy, North Dakota State University

December 8, 2025

David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?

By Shashwat Shankar, Indian Institute of Technology

December 5, 2025

RoMe: Row Granularity Access Memory System for Large Language Models

By Hwayong Nam, Seoul National University

December 3, 2025

Analog Foundation Models

By Julian Büchel, IBM Research

December 2, 2025

Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators

By Jason Yik, Harvard University

December 1, 2025

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

By Muhammed Yildirim, Ihsan Dogramaci Bilkent University

November 28, 2025

Exclude Smart in Functional Coverage

By Shailesh Vasekar, Neurotech Circuits

November 27, 2025

A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

By Jonas Elmiger, ETH Zurich

November 27, 2025

Towards a Formal Verification of Secure Vehicle Software Updates

By Martin Slind Hagen, Chalmers University of Technology

November 25, 2025

Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training

By Yipeng Wang, University of Texas

November 24, 2025

Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security

By Saumitra Jagdale, Open Cloudware

November 24, 2025

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration

By Arya Parameshwara, PES University

November 20, 2025

Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing

By Thorben Schey, University of Stuttgart

November 19, 2025

Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting

By Divya Kiran Kadiyala, Georgia Institute of Technology

November 18, 2025

FengHuang: Next-Generation Memory Orchestration for AI Inferencing

By Jiamin Li, Microsoft Research

November 17, 2025

CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage

By Nowfel Mashnoor, University of Central Florida

November 14, 2025

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices

By Arya Parameshwara, PES University

November 11, 2025

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

By Maximilian Kirschner, FZI Research Center for Information Technology

November 10, 2025

AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing

By Mohsen Ahmadzadeh, KU Leuven

November 6, 2025

FeNN-DMA: A RISC-V SoC for SNN acceleration

By Zainab Aizaz, University of Sussex

November 4, 2025